Part Number: AM2634-Q1
Hi all,
For data exchange between different cores, the AM2634-Q1 supports both IPC and shared memory approaches.
What are the advantages and disadvantages of these two methods, and in what scenarios are they each recommended?
If we need to consider functional safety, fast access within 1 ms, and hardware signal integrity, which method would you recommend?
Are there any introductory documents or examples available for these two approaches?
Regards,
Jenney
Hi Jenney,
For data exchange between different cores, the AM2634-Q1 supports both IPC and shared memory approaches.
Yes, this is right.
What are the advantages and disadvantages of these two methods, and in what scenarios are they each recommended?
IPC Notify: Hardware mailbox with interrupt. Best for events, synchronization, safety-critical signaling.
Shared Memory: Direct memory access with spinlock. Best for high-bandwidth data transfer.
I've tried to summarize in the below table:
Use IPC Notify When:
- Message size ≤ 28 bits (or ≤ 20 bits with SafeIPC)
- Need hardware error detection (CRC, overflow detection)
- Need predictable, deterministic latency
- Functional safety is required
- Event notifications, synchronization signals
- Command/control messages
Use Shared Memory When:
- Large data transfers (> 1 KB)
- Need maximum bandwidth (100+ MB/s)
- Need minimum latency (< 100 ns)
- Producer-consumer data buffers
- Sensor data arrays, processed results
- Non-safety-critical bulk data
Use IPC RPMessage When
- Variable-length structured messages (64 B - 4 KB)
- Need message queuing and buffering
- Linux interoperability required
- Don't need ultra-low latency (10-50 μs acceptable)
Use Combined Approach When
- Most real applications (recommended)
- IPC Notify for control plane (signaling, synchronization)
- Shared Memory for data plane (bulk data transfer)
- Clear separation of concerns
- Best balance of performance, safety, and complexity
Shared memory does not offer any support for CRC, Timestamping, In-built mutex, cache coherency support. All that has to be taken care in the application via Spinlocks, SW CRC support, while IPC driver has it.
If we need to consider functional safety, fast access within 1 ms, and hardware signal integrity, which method would you recommend?
IPC provides an option to have SafeIPC with CRC support for your safety needs. Both have latencies lower than 1ms.
I think you should evaluate a combined approach using shared memory and IPC. For detailed performance numbers of IPC, please see the SW datasheet numbers:
AM263x MCU+ SDK: Datasheet
Are there any introductory documents or examples available for these two approaches?
Please refer to the SDK examples:
AM263x MCU+ SDK: IPC Notify Echo
AM263x MCU+ SDK: IPC RP Message Echo
AM263x MCU+ SDK: IPC SafeIPC Echo
AM263x MCU+ SDK: IPC Shared Memory Mutex using Spinlock
Regards,
Shaunak
