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TMS320F28379D: TMS320F28379D ADC noise issue – Request official ADC schematic, PCB layout example and direct links

Part Number: TMS320F28379D
Other Parts Discussed in Thread: LAUNCHXL-F28379D

Dear TI Support Team,

I am developing a custom hardware board using the TMS320F28379D MCU and have encountered significant noise/interference in ADC sampling during testing. I suspect the issue is related to ADC schematic design and PCB layout practices.
To resolve this problem, could you please provide:
1.The official reference schematic for the ADC module of TMS320F28379D
2.The recommended PCB layout example/guidelines for the ADC section
3.Direct official web links to these documents for easy access

Thank you very much for your support.

  • Hi,

    The LAUNCHXL-F28379D LaunchPad schematic serves as TI's official reference design for ADC implementation [1]. There isn't a standalone "ADC reference schematic" document—the LaunchPad design is the de facto standard to follow.

    The critical ADC reference voltage circuit uses this architecture:
    • op-amps configured as voltage followers buffer the output (essential because the ADC draws high-frequency transient current spikes exceeding 1mA during conversions [2])
    • Each op-amp output passes through a 0.1Ω resistor (for op-amp stability when driving capacitive loads [3]) to a 22µF capacitor before feeding the VREFHI pins
    Critical constraint: VREFHI must always be driven externally on this device—internal reference is not an option [4].
    PCB Layout Guidelines

    The Technical Reference Manual provides an official layout example in Figure 14-1 "ADC and PGA-Related PCB Layout Example" [5]. Key practices:

    Reference Voltage Routing
    Requirement
    Implementation
    VREFHI capacitor placement
    As close as physically possible to pins—highest layout priority [6]
    Capacitor sizing
    22µF for 16-bit mode; 2.2µF acceptable for 12-bit mode [6]
    Each VREFHI pin
    Requires its own dedicated capacitor (pins not connected internally) [6]
    • Use separate AGND and DGND planes, connected at a single point directly under the MCU [7]
    • All analog components/traces reference AGND (connected to VSSA and VREFLO pins)
    • Digital components reference DGND (connected to VSS pins)
    • Maintain continuous ground planes under all signal traces—high-frequency return currents follow the path directly beneath the trace [7]
    Power Supply Isolation
    • Use ferrite beads to isolate analog (VDDA) and digital (VDD) power supplies [5]
    • Add LC filters to each power pin (VDDIO, VDD, VDDOSC)—skipping this makes circuits noticeably noisier [8]
    • Place 0.1µF and 10µF decoupling capacitors on all power pins, physically close to each pin (not just grouped schematically) [8]
    ADC Input Filtering
    • Place 220-330pF C0G/NPO capacitors on each ADC input [9]
    • Minimize I/O activity on pins adjacent to ADC inputs and VREFHI to reduce capacitive coupling [10]
    • Note: ADCINB0 has a non-disableable 100pF internal capacitor; ADCINB1 has a 50kΩ internal pulldown [10]
    To help narrow down your specific noise source, it would be useful to know: what noise frequency/pattern are you observing (correlated with PWM switching? random? power-supply ripple?), and are you currently using buffered or unbuffered reference voltage? Also, confirming whether you're operating in 12-bit or 16-bit mode affects the capacitor sizing requirements significantly.

    Citations:

    1. TI E2E Forum - LaunchPad Schematic Reference
    2. TI E2E Forum - VREFHI Current Draw
    3. TI E2E Forum - 0.1Ω Resistor Purpose
    4. TMS320F28379D Technical Reference Manual - External VREFHI Requirement
    5. TMS320F28379D Technical Reference Manual - PCB Layout Example
    6. TI E2E Forum - Signal Conditioning Recommendations
    7. TI E2E Forum - AGND/DGND Strategy
    8. TI E2E Forum - Power Supply Filtering
    9. TI E2E Forum - ADC Input Capacitors
    10. TMS320F28379D Datasheet - Pin Specifications
    11. TMS320F28379D Datasheet - PowerPAD Requirements
    Thanks
    Srikanth