TMS320F28384D: TMS320F28384D: CMPSS TRIP pin configuration

Yes — You Can Use ADCINA5/CMPIN2N for ADC Measurements. No Grounding Required.

When CMPSS2 is configured to use the internal DAC as its negative threshold, the external CMPIN2N pin is internally disconnected from the comparator circuit via an input multiplexer [1]. This means your TRIP protection is completely unaffected by whatever signal you apply to that pin, and you are free to use ADCINA5/CMPIN2N for standard ADC voltage or current measurements.

Why This Works: The Pin Architecture

The ADCINA5/CMPIN2N physical pin is routed to two independent, parallel paths inside the device:

The key is the COMPCTL.COMPDACL bit. When you configure the internal DAC as the negative reference, the multiplexer selects the DAC output and disconnects the external CMPIN2N pin from the comparator's internal circuitry [1][2]. The ADC path to the same pin remains fully operational and independent.

This architecture is explicitly documented in the TRM: pins connected to CMPSS inputs can be used for CMPSS and ADC simultaneously without any special handling.

Recommended Configuration

•  Connect your analog signal directly to ADCINA5/CMPIN2N and configure it as a normal ADC-A channel 5 input
•  No grounding needed — floating or signal-driven, the pin does not disturb CMPSS2 TRIP protection when the internal DAC is selected [2][4]
•  CMPSS2 continues to operate normally using ADCINA4/CMPIN2P as the positive input and the internal 12-bit DAC as the negative threshold

A Few Practical Considerations

Stay within the ADC input voltage range. Ensure the signal on ADCINA5 stays below VDDA + 0.3V. Exceeding this level activates an internal blocking circuit that isolates the comparator from the external pin, which could cause incorrect comparator output — and it can also disturb the internal VREF, potentially affecting other ADC or DAC channels sharing the same reference [5].

Set adequate ACQPS for ADC settling. When sampling on ADCINA5, configure a sufficient acquisition window (ACQPS) to allow the input circuit to fully settle, especially if your signal source has non-negligible impedance. The ADC input model and sample capacitor values in the TRM ADC chapter can help you calculate the minimum required acquisition time [6].

Minimize switching noise on adjacent pins. As a PCB best practice, reduce I/O switching activity on pins adjacent to your ADC inputs to limit capacitive coupling and crosstalk [5]. Since ADCINA4 and ADCINA5 are physically adjacent, this is worth keeping in mind if your current sensing signal has fast transients.

ADC-to-ADC isolation. If you sample ADCINA4 and ADCINA5 synchronously, be aware of the ADC-to-ADC isolation specification of ±2 LSBs (at VREFHI = 2.5V) for the TMS320F28384D [5].

If you'd like further guidance, it would help to know: (1) the voltage range and source impedance of the signal you plan to measure on ADCINA5, to confirm ACQPS sizing; (2) whether you need to sample ADCINA4 and ADCINA5 simultaneously, which affects SOC configuration; and (3) whether there is significant high-frequency switching activity near these pins on your PCB that might warrant additional filtering.

Citations

1. TMS320F2838x Technical Reference Manual (SPRUII0F) – CMPSS Chapter, p. 2803/2554/2555
2. E2E: TMS320F28388D – Multiple Phase Leg Interleaved Peak Current Control
3. TMS320F2838x Technical Reference Manual (SPRUII0F) – Analog Subsystem, p. 2553
4. E2E: TIDM-02002 – Resetting CTRIPH/CTRIPL Twice Within a PWM Cycle
5. TMS320F28384D Datasheet (SPRSP14E) – ADC Electrical Specifications, p. 157–158/170
6. E2E: TMS320F28384D – Unknown Frequency Noise at ADC Input

Best Regards,

Zackary Fleenor