F29H859DU-Q1: F29 RTDMA update issue

Kita Li

Hi experts,

My customer wants to realize the following requirement with F29: PWM triggers ADCSOC0, ADCSOC1, ADCSOC2 conversion periodly, after the last ADC conversion, use DMA to move these 3 adc results in a RX buffer. In the next time trigger, also use DMA to move new adc results in a RX buffer with address offset that will not cover the last time value. After the buffer is full, then the new result will cover the old result from beginning of buffer.

In order to realize this function, customer sets burst size as 6, Transfer size as 1, Destination Address Burst Step as 2, Destination Address Transfer Step as 6. But we checked the buffer, every triggered result will be only updated in first 6 bytes of buffer. You can refer to the attached demo file: rtdma_academy_lab_test.zip

Could you check what's error that causes this issue?

Best Regards

Kita

5 months ago

0 Aishwarya Rajesh 5 months ago

TI__Mastermind 20745 points

Hi Kita,

Let me test this code on my end and determine what's the most straightforward solution here. Will have a response in the next day or two.

Best Regards,

Aishwarya

0 Kita Li 4 months ago in reply to Aishwarya Rajesh

TI__Expert 3585 points

Hi Aishwarya,

Is any update on this question?

Best Regards

Kita

0 Kita Li 4 months ago in reply to Aishwarya Rajesh

TI__Expert 3585 points

Hi Aishwarya,

Is any update on this question?

Best Regards

Kita

0 Aishwarya Rajesh 4 months ago

TI__Mastermind 20745 points

Kita,

Apologies for the delay, I will have an update within the day.

Best Regards,

Aishwarya

0 Aishwarya Rajesh 4 months ago

TI__Mastermind 20745 points

Kita,

Apologies for the delay. The issue is that the Source Address Burst Step was set to 0 which was signaling the DMA to read from only ADCRESULT0 instead of incrementing to the remaining result registers.

BTW, the interrupt is configured to occur at the beginning of the transfer, so keep that in mind when viewing results.

Best Regards,

Aishwarya

0 Kita Li 4 months ago in reply to Aishwarya Rajesh

TI__Expert 3585 points

Hi Aishwarya,

Sorry for late reply, let me clarify the request here: In current project, in the next time trigger, customer wants to use DMA to move new adc results in a RX buffer with address offset that will not cover the last time value.

But in the test, only the first 3 buffer will have value, other buffers are still empty. Their requirement is: ADC always sampling, then result can be move to AdcBufRaw until it's full. Once full, then store the new data again from the beginning of AdcBufRaw.

We tried the suggestion you provided, it still can't work. And we think this is the destination issue.

Best Regards

Kita

0 Aishwarya Rajesh 4 months ago

TI__Mastermind 20745 points

Kita,

I understand now. Let me take a look at this and get back to you by the end of the week. I just want to try this on my end quickly.

Best Regards,

Aishwarya

0 Kita Li 4 months ago in reply to Aishwarya Rajesh

TI__Expert 3585 points

Hi Aishwarya,

Is any update on the test?

Best Regards

Kita

0 Aishwarya Rajesh 4 months ago

TI__Mastermind 20745 points

Kita,

Sorry, please give me one more day to test this on my end.

Best Regards,

Aishwarya

0 Kita Li 4 months ago in reply to Aishwarya Rajesh

TI__Expert 3585 points

Hi Aishwarya,

Is there any update on this issue?

Best Regards

Kita

0 Delaney Woodward 4 months ago in reply to Kita Li

TI__Mastermind 26090 points

Hi Kita,

Aishwarya is currently out of office until next week. Please expect a delayed response.

Best regards,

Delaney

0 Aishwarya Rajesh 4 months ago

TI__Mastermind 20745 points

Kita,

I'm sorry for the delay, I'm still trying to figure it out with your exact settings. We do have this example, which is similar to your use case, if you want to take a look at in the mean time: C:\ti\c2000\f29h85x-sdk_1_03_00_00\examples\driverlib\single_core\adc\adc_ex6_continuous_dma

Best Regards,

Aishwarya

0 Kita Li 3 months ago in reply to Aishwarya Rajesh

TI__Expert 3585 points

Hi Aishwarya,

we refer to demo and change based it, but still fails. So need to figure out the root cause.

Best Regards

0 Aishwarya Rajesh 3 months ago

TI__Mastermind 20745 points

Kita,

Thanks for checking, I am checking with our design team on a question and will get back to you ideally by Thursday morning. I really do appreciate your patience here as we figure it out.

Best Regards,

Aishwarya

0 Aishwarya Rajesh 3 months ago

TI__Mastermind 20745 points

Kita,

I'm meeting with the design team my morning tomorrow and will have an update for you afterwards.

Best Regards,

Aishwarya

0 Aishwarya Rajesh 3 months ago

TI__Mastermind 20745 points

Kita,

Good news, we figured it out. The following needs to be modified: Transfer Size, Source Wrap Size, Source Address Wrap Step, and Destination Address Transfer Step.

Transfer size is configured as 32 bursts * 6 bytes per burst = 96 bytes assuming a destination buffer length of 96.
Source Wrap Size is 1 because after every 1 transfer, the DMA needs to wrap back to the beginning to the start of ADCRESULT0.
Source Address Wrap Step is 0 because when wrapping back to the beginning, there is no need to increment the address.
Destination Address Transfer Step is 2 because after writing 6 bytes / 3 16-bit values, DMA needs to increment 2 bytes to start writing to the next 3 slots.

For testing purposes, I also used the "DMA interrupt is generated at the end of a transfer" interrupt mode. Once again, I apologize for the delay.

Best Regards,

Aishwarya

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F29H859DU-Q1: F29 RTDMA update issue