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F28377D-SEP: ADC acquisition

Reshma M
Prodigy 40 points

Part Number: F28377D-SEP
Other Parts Discussed in Thread: TMS320F28388D

I'm using TMS320F28388D MCU for my operation. 

According to the ADC acquisition specification, a minimum of 4 acquisition cycles is required to obtain an accurate ADC reading. If the acquisition value is set below this minimum, the accuracy is not guaranteed.

I would like to understand the impact of this condition in more detail. If high switching activity introduces noise in the system when the minimum acquisition number is used, which bits of the ADC output are typically affected? Does the noise primarily impact the LSBs, the MSBs, or both? Also, does this error manifest symmetrically in both the positive and negative directions?

Additionally, if external noise sources have already been minimized but conversion errors are still observed with the minimum of 4 acquisition cycle, by how much should the acquisition time be increased to ensure stable and accurate readings?

  • 0
    Prodigy 40 points

    Also wanted to know if the below points are valid?

    • ADC module can be split between the two cores. Once the ADC module is owned by one core, all the channels in that module is owned by that core. It cannot be split.
    • Despite two cores, ADC conversion in parallel can only happen 4 at any given point of time.
  • 0 in reply to Reshma M
    TI__Expert 7270 points

    Hello Reshma,

    When the sampling capacitor doesn't have sufficient time to charge, errors primarily affect the LSBs rather than the MSBs. To achieve rated resolution, the signal source must charge the internal sampling capacitor to within 0.5 LSB of the true signal voltage.  insufficient acquisition time means this settling criterion isn't met, and the residual error shows up in the lower-order bits first.

    The 4-cycle minimum you reference actually corresponds to the 75 ns absolute minimum sample window specified in the datasheet. This minimum assumes a low source impedance (≤50 Ω) and a clean signal environment. If there are external noises, increase Acquisition window to 200-300ns. You could keep increasing Acquisition window until signal gets full settled.

    ADC module ownership cannot be split: Once an ADC module is assigned to a core, all channels within that module belong to that core.  By default, all peripherals including ADC modules are owned by CPU1

    The TMS320F28388D has exactly four independent ADC modules. Each module contains a single sample-and-hold (S/H) circuit, meaning conversions within a single module are always sequential. Since there are only 4 S/H circuits across the entire device, the maximum number of truly simultaneous conversions is 4 — regardless of whether you're using one core or both.

    Note: Also confirm whether you're operating in 12-bit or 16-bit mode, as the 16-bit mode minimum acquisition window is 320 ns

  • 0 in reply to Stevan Duraskovic
    Prodigy 40 points

    Hi Stevan,

    Thank you for the reply, it resolved most of my doubts.

    In the datasheet, it has been mentioned that there are gain error and offset error, etc. Considering both gain and offset error occurs at the same time, then more LSBs are going to get affected. Will increasing the acquisition time help during this case?

    In the calculation of acquisition time example mentioned in TRM, the rated value of all the resistors and capacitors are mentioned except of Cs in the datasheet. What should I consider for this?

    Regards,
    Reshma.

  • +1 in reply to Reshma M
    TI__Expert 7270 points

    Hello Reshma,

    Cs is part of the signals RC (RsCs) network going into the ADC. Increasing acquisition time will not help with gain and offset errors. You would need to perform gain and zero offset calibration as outlined in the TRM.

  • 0 in reply to Stevan Duraskovic
    Prodigy 40 points

    Thanks Stevan!

  • 0 in reply to Reshma M
    TI__Expert 7270 points

    Glad I could help!

  • 0 in reply to Stevan Duraskovic
    Prodigy 40 points

    I have made a table for ADC including the worst case scenarios. Can you please verify if my understanding is correct?

    *From the datasheet the calculated value is lesser than 320ns, however, the minimum acquisition time is 320ns. Hence this number is taken for calculations.

    ^The minimum acquisition time for a 12 bit ADC is 75ns, however, the worst-case scenario value calculated with the numbers from the data sheet is 109ns.

  • 0 in reply to Reshma M
    TI__Expert 7270 points

    Hello Reshma,

    I will take a look at the table and reply in timely manner.

  • +1 in reply to Reshma M
    TI__Mastermind 35383 points

    Hi Reshma,

    Thanks for compiling that detailed table – it’s great to see you’ve put in the effort to analyze the ADC parameters so thoroughly! It shows a strong understanding of the requirements.

    Regarding your questions about acquisition time and accuracy, let’s dive a bit deeper. As Stevan pointed out, insufficient acquisition time primarily impacts the LSBs of the ADC output. The internal sample-and-hold capacitor needs time to charge, and if it doesn’t settle fully, the resulting error shows up in the lower-order bits first. The error isn’t necessarily symmetrical and could be biased in either direction.

    Determining Optimal Acquisition Time:

    While the datasheet specifies minimum acquisition times (75ns for 12-bit, 320ns for 16-bit), those are under ideal conditions. Your calculated values of 109ns (12-bit) and 320ns (16-bit) based on your circuit parameters are a much better starting point. I recommend these steps to fine-tune it:

    1. Start with your calculated worst-case acquisition time.
    2. Measure the ADC output for a stable DC voltage and collect a large number of readings (e.g., 1000).
    3. Analyze the data: Look at the mean (to identify offsets), standard deviation (to quantify noise/instability), and a histogram for distribution.
    4. Incrementally increase the acquisition time (e.g., 50-100ns) and repeat the measurements until acceptable accuracy and stability are achieved. There is a point of diminishing returns, so don’t overdo it.

    Regarding Gain & Offset Errors:

    You are correct that gain and offset errors affect multiple LSBs. Increasing the acquisition time will not address these errors. You’ll need to implement the gain and offset calibration procedures outlined in the TRM.

    Cs Value (Sampling Capacitor):

    You rightly pointed out that the TRM calculation is missing the Cs value. Please refer to the ADC module section of the datasheet for the precise value of the sampling capacitor. Confirming the datasheet value is crucial for accurate calculations.

    To recap, focus on using your calculated worst-case acquisition times as a starting point, and then iteratively test to find the optimal setting for your application and environment.

    Let us know if you have any further questions or need clarification on any of these points.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 40 points

    Got it Zackary!
    Thank you so much for taking time to go through the table and helping me understand things better.

    Regards,
    Reshma.