• State TI Thinks Resolved
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 44 views
  • Users 0 members are here
Support feedback
Options
Options
Related

F28377D-SEP: ADC acquisition

Reshma M
Prodigy 10 points

Part Number: F28377D-SEP
Other Parts Discussed in Thread: TMS320F28388D

I'm using TMS320F28388D MCU for my operation. 

According to the ADC acquisition specification, a minimum of 4 acquisition cycles is required to obtain an accurate ADC reading. If the acquisition value is set below this minimum, the accuracy is not guaranteed.

I would like to understand the impact of this condition in more detail. If high switching activity introduces noise in the system when the minimum acquisition number is used, which bits of the ADC output are typically affected? Does the noise primarily impact the LSBs, the MSBs, or both? Also, does this error manifest symmetrically in both the positive and negative directions?

Additionally, if external noise sources have already been minimized but conversion errors are still observed with the minimum of 4 acquisition cycle, by how much should the acquisition time be increased to ensure stable and accurate readings?

  • 0
    Prodigy 10 points

    Also wanted to know if the below points are valid?

    • ADC module can be split between the two cores. Once the ADC module is owned by one core, all the channels in that module is owned by that core. It cannot be split.
    • Despite two cores, ADC conversion in parallel can only happen 4 at any given point of time.
  • 0 in reply to Reshma M
    TI__Expert 6100 points

    Hello Reshma,

    When the sampling capacitor doesn't have sufficient time to charge, errors primarily affect the LSBs rather than the MSBs. To achieve rated resolution, the signal source must charge the internal sampling capacitor to within 0.5 LSB of the true signal voltage.  insufficient acquisition time means this settling criterion isn't met, and the residual error shows up in the lower-order bits first.

    The 4-cycle minimum you reference actually corresponds to the 75 ns absolute minimum sample window specified in the datasheet. This minimum assumes a low source impedance (≤50 Ω) and a clean signal environment. If there are external noises, increase Acquisition window to 200-300ns. You could keep increasing Acquisition window until signal gets full settled.

    ADC module ownership cannot be split: Once an ADC module is assigned to a core, all channels within that module belong to that core.  By default, all peripherals including ADC modules are owned by CPU1

    The TMS320F28388D has exactly four independent ADC modules. Each module contains a single sample-and-hold (S/H) circuit, meaning conversions within a single module are always sequential. Since there are only 4 S/H circuits across the entire device, the maximum number of truly simultaneous conversions is 4 — regardless of whether you're using one core or both.

    Note: Also confirm whether you're operating in 12-bit or 16-bit mode, as the 16-bit mode minimum acquisition window is 320 ns