TMS320F28069: Max. ADC Clock Value for TMS320F28069 Controller

Hi Nikileshwar,

If you leave ADCCTL2 unconfigured (at its default reset value), your ADC clock will be 80 MHz — which exceeds the maximum rated ADC clock of 45 MHz and will cause unreliable operation.

Here's why:

The ADCCTL2 register resets to 0x0000, meaning both CLKDIV2EN and CLKDIV4EN default to 0 [1]. Per the clock divider truth table in the TRM:

With both bits at 0 (default), ADCCLK = SYSCLK = 80 MHz [1]. Since the datasheet specifies a maximum ADC clock of 45 MHz [2], this default configuration violates the device's operating limits.

You Must Configure ADCCTL2

Set CLKDIV2EN = 1 to divide your 80 MHz SYSCLK by 2, giving you a 40 MHz ADC clock — safely within the 45 MHz limit:

EALLOW;
AdcRegs.ADCCTL2.bit.CLKDIV2EN = 1; // ADCCLK = 80 MHz / 2 = 40 MHz
AdcRegs.ADCCTL2.bit.CLKDIV4EN = 0;
EDIS;

Why This Matters

Multiple users have reported severe ADC issues when exceeding the 45 MHz limit, including abnormal jitter, unstable readings [3], and significant non-linearity with output "plateaus" [4]. A TI engineer confirmed that the ADC state machine is not validated for operation above 45 MHz — increasing the sample-and-hold window does not compensate for this; the constraint is on the ADC clock itself [5].

1. TMS320x2806x Technical Reference Manual - ADCCTL2 Register (SPRUH18I, p.537)
2. TMS320F2806x Datasheet - ADC Electrical Characteristics (SPRS698J, p.37)
3. E2E: ADC clock frequency discussion on TMS320F28069
4. E2E: TMS320F28069 ADC non-linearity problem
5. E2E: TMS320F28069 1MHz ADC sampling frequency question

Best Regards,

Zackary Fleenor

Hi Nikileshwar,

The default value (aka value after reset) is defined in the register bitfield table of the TRM register sections:

Best Regards,

Zackary Fleenor

Hi Fleenor, 

Thanks for your support. My doubts are clarified.