Part Number: TMS320F280039C
I have an application that configures the MCAN module to use Rx FIFO 1 in overwrite mode. When the FIFO runs into full condition, the Rx FIFO Full bit (MCAN_IR.RF1F) is set as expected. When another message is received and the oldest FIFO entry is overwritten (lost), the Message Lost bit (MCAN_IR.RF1L) is not set.
However, when I configure Rx FIFO 1 in blocking mode, the FIFO full bit is set when the buffer is full and the Message Lost bit is set, when another message is received (and lost).
Is this the normal behaviour or is this a bug?
Thank you,
Markus