TMS320F28035-EP: TMS320F28035MPNTEP - External ADC Reference : ADCINA0 Pin

We are observing a lot of drift on ADC Count value of ADCINA0 channel even though there is stable voltage at ADC Input.

Hey Asha,

Thanks for providing the additional information.

One important detail to confirm: your part number TMS320F28035MPNTEP indicates the 80-pin PN package. The answer to your question depends critically on which package you're using, because the pin mapping differs between packages. I'll address both scenarios below.

ADCINA0 Limitation in External Reference Mode

The answer depends on your package:

80-pin PN package (your part number suggests this): ADCINA0 (pin 18) and VREFHI (pin 19) are separate physical pins [1]. This means you can use ADCINA0 as an ADC input channel even in external reference mode — there is no conflict.

64-pin PAG or 56-pin RSH packages: VREFHI and ADCINA0 share the same physical pin, making their use mutually exclusive [1]. When external reference mode is enabled (ADCREFSEL = 1), ADCINA0 becomes dedicated to the reference voltage input and cannot be used for conversions [2][3].

If you are indeed using the 80-pin PN package, the ADCINA0 channel should function normally in external reference mode. Please confirm your package to rule this out as the cause of your drift issue.

Addressing the ADC Drift on ADCINA0

Since you're observing significant drift despite a stable input voltage, the likely causes are ADC offset and gain error — both of which are inherent to this device and temperature-dependent:

• Offset error: Specified at ±20 LSBs with one-time calibration. Periodic offset calibration (sampling the internal VREFLO connection and adjusting the trim register) reduces this to ±4 LSBs [4].
• Gain error: ±40 LSBs with external reference, and this is the dominant error source for this ADC. The temperature coefficient is typically −20 ppm/°C [5]. Gain error can be reduced to approximately ±7.2 LSBs through periodic single-point gain calibration using a precision external voltage source [4].
• DC code spread: This ADC has a natural noise spread of ~4 LSBs. Averaging 256 samples or more is recommended to reduce noise to ~0.25 LSBs [4].

Recommended Actions

1. Implement periodic offset calibration — sample the internal VREFLO connection periodically and adjust the offset trim register. This requires no external pin and is handled in hardware [4].
2. Implement periodic gain calibration — provide a precision calibration voltage near full-scale on a spare ADC channel and correct gain in software [4].
3. Verify signal source impedance — the ADC input is a switched-capacitor circuit, so a high-impedance source or insufficient acquisition time (ACQPS) will cause settling errors that appear as drift or noise [6].
4. Verify external reference stability — ensure your external VREFHI source is properly buffered and decoupled. A precision reference like REF5030 buffered by an OPA320 is recommended [4].
5. Average multiple samples — to suppress the inherent ~4 LSB code spread.

To help diagnose further, it would be useful to know: the magnitude of drift you're seeing (in LSBs or mV), your operating temperature range, your ACQPS setting, and whether any periodic calibration is currently implemented.

Sources:

1. TMS320F28035 Datasheet - Pin Assignments
2. TMS320F2803x Technical Reference Manual - ADC Reference
3. TMS320F2803x Technical Reference Manual - ADCREFSEL
4. TI E2E: TMS320F28035 ADC Calibration and Total Unadjusted Error
5. TMS320F28035 Datasheet - ADC Electrical Characteristics
6. TI E2E: TMS320F28035 ADC Input Model and Reference

Best Regards,

Zackary Fleenor

Hello Fleenor,

Thank you for the response.

We are using LQFP 80 Pin Package. 

We are going through the other points which you have highlighted. Will get back to you on this!

Regards,

Asha C