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TMS320F28P550SG: Obscure behaviour of phase offsetted and synced EPWM-timer when counter is written by code

Marco Schlüter
Prodigy 120 points

Part Number: TMS320F28P550SG

Hello guys,

I have an errouness behaviour I would like to share of a pwm-timer with this setup:
 - having pwm8 synced to pwm7 (sync on zero) with a phase offset for pwm8 of half the period to get 180 degree offset between pwm8 and 7
 - period at 3500 to get 40kHz pwm (up-counting) with the controller running at 140MHz (that means pwm8 phase offset of 1750)
 
I set the pwm8-counter to the phase offset of 1750 within the init phase when pwm-counters alre still stopped to have both timers run in sync and offsetted from the very beginning.
With this setup the pwm8-ctr counts repeatingly from 1750 to 5250 (3500 + 1750) and never comes to 0 whatsoever. It seems as if the pwm8-ctr is forever offsetted with its initial ctr val before it started running.
Without setting the ctr value before start this does not occur.
When clearing the phase to 0 once this strange behaviour occurs the pwm8 counter is kind of repaired and I cna then apply the phase offset again to have the pwm8 ctr behave the way I expect.

  • 0
    TI__Mastermind 19026 points

    Hi,

    Make sure you followed the correct sequence of PWM time base sync by disabling clocks first then initialize PWM and then start PWM clock.

    Marco Schlüter said:
    With this setup the pwm8-ctr counts repeatingly from 1750 to 5250 (3500 + 1750) and never comes to 0 whatsoever

    PWM counter will never exceed PRD, not sure what you mean by above.

    Please refer to the C2000 Ware example to understand the phase delay demo. If you still have questions please come up with specific diagram sequence that you followed to understand the issue in detail.

    Thanks

  • 0 in reply to Prarthan Bhatt
    Prodigy 120 points

    Hi Prarthan,

    I did follow the correct sequence of PWM syncing and starting.

    I know that the PWM counter will never exceed the PRD value in every situation but this seems to me like an error situation. I did make you a screenshot of the CCS window with stopped controller in our normal application.

  • 0 in reply to Marco Schlüter
    TI__Mastermind 19026 points

    Hi,

    The TBPHS if greater than TBPRD it can cause TBCTR to jump to value higher than TBPRD on sync event and count up or down based on sync cntr direction configured.

    Or if the TBCTR register was itself written to value higher than TBPRD. Are you changing TBPRD value also over time or is it static ?

    Based on implementation, if the PRD == CNTR then the CNTR value is reset. If you are seeing the value higher than PRD in cntr means something is modifying TBCTR to be larger than PRD. 

    Thanks

  • 0 in reply to Prarthan Bhatt
    Prodigy 120 points

    As this does not occur when I skip writing the counter value directly with the phase value during the init phase I have a solution for my code.

    Thanks for your help.