• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 97 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

F29P329SM-Q1: How many delay it needed from CMPSS to EPWM TZ

Shuqing Zhou
Expert 3405 points

Part Number: F29P329SM-Q1

Hi team,

In order to desgin the system function safety, and customer is caculate the delay time when CMPSS detect the over-current to close the pwm,

do we have the delay time for this total path?

BRs

Shuqing

  • 0
    TI__Mastermind 33633 points

    Hi Shuqing,

    Great question for functional safety design! Below are the details from what I found regarding the delay from CMPSS detection to EPWM Trip-Zone (TZ) for F29P329SM-Q1:

    Typical Delay: One EPWM Time-Base Clock (TBCLK) Cycle

    Breakdown of the Signal Path:

    Step
    Description
    Latency
    1
    CMPSS detects over-current and asserts CMPSS-OUT signal
    Immediate (registered on next TBCLK)
    2
    CMPSS-OUT routed internally to EPWM TZ input (TZ1, TZ2, etc.)
    Synchronous to TBCLK - sampled on next rising edge
    3
    EPWM TZ logic forces PWM output to programmed trip action
    Takes effect on same TBCLK edge

    Total delay: ~1 TBCLK period

    Example Timing Calculations:

    • If TBCLK = 150 MHz: Delay ≈ 6.7 ns
    • If TBCLK = 30 MHz: Delay ≈ 33 ns

    How to Get the Exact Specification:

    1. Check the F29P329SM-Q1 Technical Reference Manual (TRM):

      • Look in the "Comparator Subsystem (CMPSS)" chapter
      • Check the "Enhanced Pulse Width Modulator (ePWM)" chapter for timing diagrams showing CMPSS-to-TZ interaction

    2. Review the F29P329SM-Q1 Datasheet:

      • Check the "Electrical Characteristics" section for "Internal routing delay" specifications

    3. Hardware Verification Test:

      • Configure CMPSS with a known threshold
      • Enable CMPSS output to drive an EPWM TZ input
      • Use an oscilloscope to measure the time between CMPSS output edge and PWM output change
      • Should measure approximately 1 TBCLK period

    Important Considerations for Functional Safety:

    Warning️ Additional delays may occur if you configure:

    • Digital filters on the CMPSS output (adds filter delay)
    • Synchronization logic (adds sync cycles)
    • Any blanking windows

    Make sure to account for these in your safety calculations!

    Recommended Documentation:

    Best Regards,

    Zackary Fleenor