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TMS320C28345: C28p65 Dual core CPU2 Debug Issue

Jwalant Dholakia
Prodigy 60 points

Part Number: TMS320C28345
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

I am using TMS320F28P650DK9  ControlCard as the development platform with CCS 20.4 as the IDE.

Also, my reference is https://software-dl.ti.com/C2000/docs/C2000_Multicore_Development_User_Guide/debug.html#loading-program-in-multiple-cores

My steps for a debug session is -

  1. Launch a dual-core project-less debugging session,
  2. Connect to CPU1 and halt it
  3. Connect to CPU2 and halt
  4. Load Program (.out file) in CPU1 and run the program (to allow CPU2 booting)
  5. Load program on CPU2.

When I pause or put a breakpoint on CPU2 side, it is always stuck at 0x3FAA42 location with infinite loop and never makes to main. 

Here is how the session looks like when the issue occurs 

image.png

My Target config file for Debug is 

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
    <configuration XML_version="1.2" id="configuration_0">
        <instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
        <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
            <instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds510c28x.xml" id="drivers" xml="tixds510c28x.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds510cla2.xml" id="drivers" xml="tixds510cla2.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds510cs_child.xml" id="drivers" xml="tixds510cs_child.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds510ajsm.xml" id="drivers" xml="tixds510ajsm.xml" xmlpath="drivers"/>
            <property Type="choicelist" Value="3" id="SWD Mode Settings"/>
            <platform XML_version="1.2" id="platform_0">
                <instance XML_version="1.2" desc="TMS320F28P650DK9" href="devices/f28p650dk9.xml" id="TMS320F28P650DK9" xml="f28p650dk9.xml" xmlpath="devices"/>
                <device HW_revision="1" XML_version="1.2" description="" id="TMS320F28P650DK9" partnum="TMS320F28P650DK9">
                    <router HW_revision="1.0" XML_version="1.2" description="ICEPick_C router" id="IcePick_C_0" isa="ICEPICK_C">
                        <subpath id="Subpath_1">
                            <property Type="numericfield" Value="0x11" desc="Port Number_0" id="Port Number"/>
                            <cpu XML_version="1.2" id="C28xx_CPU2" HW_revision="1.0" isa="TMS320C28xx" description="C28xxCPU">
                                <property id="Slave Processor" Type="choicelist" Value="1"/>
                            </cpu>
                        </subpath>
                        <subpath id="Subpath_0">
                            <cpu XML_version="1.2" id="C28xx_CPU1" HW_revision="1.0" isa="TMS320C28xx" description="C28xxCPU">
                                <property id="Slave Processor" Type="choicelist" Value="0"/>
                            </cpu>
                        </subpath>
                    </router>
                </device>
            </platform>
        </connection>
    </configuration>
</configurations>
 
Pl. help by providing a reliable way to debug on CPU2
  • 0
    TI__Expert 3250 points

    Hi, 

    Jus a few questions,

    1. Are you attempting RAM or Flash based debugging?

    2. Is this project an example from our SDK? Can you attempt a multi-core example from our SDK 

    3. Are you using RAM or Flash to debug this project?

  • 0 in reply to AJ Favela
    Prodigy 60 points

    1. RAM

    2. Yes, it is based on C28_dual empty project example found withing C2000Ware for p65 family of DSPs.

    3. RAM

  • 0 in reply to Jwalant Dholakia
    TI__Expert 3250 points

    Hi Jwalant,

    Can you attempt a different example such as ipc_ex3_basic_sysconfig? 

    When attempting this example do the following steps:

    1. Launch a dual-core project-less debugging session,
    2. Connect to CPU1 and then CPU2
    3. Load CPU1.out to CPU1 and let it run
    4. While CPU1 is running load CPU2.out to CPU2

    CPU2's file should start at main and allow you to step though the code. Additionally you should be able to set breakpoints as you please.

    Also please check that when you start a project-less debugging session, you toggle active breakpoints under the breakpoints section 

  • 0 in reply to AJ Favela
    Prodigy 60 points

    This approach seems to be working. Can you recommend how to automate some of that through GEL file or some other method? Thank you.