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AM13E23019: Cache pre-fetch performance on multiple motor control

Joe Ji
Expert 4350 points

Part Number: AM13E23019

Hi Expert

AM13E230 has 1K Cache which can do pre-fetch on CPU instruction, idealy the pre-fetch instruction can be all accepted by CPU but when there are more motors like 1 MCU for 2 or 4 motors, the interrupts get more random, customer want to know in multiple motor control use case, will the cache pre-fetch function performance be worse? How it effect the CPU running efficiency?

Thank

Joe

  • +1
    TI__Intellectual 1150 points

    Hi Joe,

    In multi-motor systems, if each motor is controlled by independent asynchronous interrupts, the instruction stream becomes non-sequential. This reduces prefetch effectiveness and increases cache miss rate, leading to inconsistent CPU efficiency.

    However, this impact can be significantly mitigated by:

    • Scheduling all motor control loops within a single synchronized ISR
    • Keeping the control code compact and contiguous so there cab be certainity in cache hits.

    But, for overall consistent behavior, we would recommend to execute the time critical foc loops from the RAM there by operations are much efficient always without cache dependency.