GPIO Config problem?

Have you used the M3 to give C28 control of the GPIO pins? As master, M3 controls the clocking and major configuration of the GPIO pins.  The setup_m3 project in controlSUITE device_support under "Control" examples shows how this is done in code via driverlib function calls.

M3 must first:

1. Enable the GPIO port (GPIO11 would be within GPIOB on the M3 side). This includes clocking the GPIO port.
2. Configure the GPIO port for C28 to control (again, GPIO11 would be within GPIOB on the M3 side). 

C28 should then remember to:

1. Use EALLOW; (GPIO config registers are EALLOW-write protected).
2. Configure GPIO11 as output.
3. Use EDIS; (optional - to turn off the EALLOW-write protection)
4. Use GPIO11..- i.e. toggle/set/clear/etc.

Make sure that the above are done properly in code and then see if it works..

OK, partly fixed.  GPIO11 was assigned to the M-core.  Now I can toggle that IO pin from the C28.  

So that "sanity check" is working, but I still can't get the ePWMs to affect the IO pins.

For example, I'm using ePWM9, with EPWM9A on GPIO62 (M-core J6) and EPWM9B on GPIO63 (M-core J7).  With the debugger register view, I've verified these settings:

I assume PortJ is enabled because this pin functions when I run the BLDC example, using the same M3-Setup function.  And I'm using TI's function call      SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); 

Core Select is set to C-core: 
M-core  GPIO_PORTJ.GPIOCSEL = 0x000000EE

In the C-core, they are set to operate as PWM:
GPIOG1CTRL.GPBMUX2 = 0xFC740550 

In the C-core, they are set as OUTPUT:
GPIOG1CTRL.GPBDIR = 0xE6000000 

The PWM Action Qualifier for output A is set to CAU_SET + CAD_CLEAR.  
 ePWM9.AQCTLA = 0x0060

The B output is set to no action.
 ePWM9.AQCTLB = 0x0000

The PWM counter is changing.  The compare register CMPA is getting updated by the program.  The Time Base Status Register , TBSTS, seems to alternate between values 2 and 3.  All software override registers are cleared:
ePWM9.AQSFRC = 0x0000
ePWM9.AQCSFRC = 0x0000

But I still have no change occurring in the data register.  (I do see changes in GPADAT, from toggling GPIO11 as discussed above)
GPIOG1DAT.GPBDAT =  0x023C0000  constantly

I've also tried to get the output to change by forcing the software override like this, inside main() loop:

 #define EPwmMotrCRegs EPwm9Regs

 i++;
 if( i==50 )
 {
 EPwmMotrCRegs.AQCSFRC.bit.CSFA = CSFB_HIGH; // Force EPWM9A HIGH
 }
            
 if( i>=100 )
 { 
 EPwmMotrCRegs.AQCSFRC.bit.CSFA = CSFA_LOW; // Force EPWM9A LOW
 i=0;
 }  

Unfortunately, still no change on the output pin or GPBDAT register.

What am I missing?

Thanks,
-Will

Hi Chrissy,

I appreciate your kind help for helping Will who is my customer in the south. He is facing a very tight schedule right now and he needs to tackle this obstacle in order to move forward. I hope you can give some priority in supporting Will with his current issue so he can use the weekend to get the project on track. Thanks again.

Regards,

Jason

Jason,

I have attached a config code snippet for customer below. This is just an sample although there are multiple modes in which he can operate this module, atleast will help us flush any peripheral setup issues. if there is configurations followed along the same lines as below and still issue persists we will suggest some GPIO sample code

   EALLOW; // This is needed to write to EALLOW protected registers

   SysCtrlRegs.PCLKCR2.bit.EPWM9ENCLK = 1;  // enable clock to EPWM9  
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC  = 1;  // all TBs - start counting

   // Setup TBCLK
   EPwm9Regs.TBCTL.bit.CTRMODE = 0x2;       // Count up/down
   EPwm9Regs.TBPRD = 2000;                 // Set timer period, Please input desired time base period
   EPwm9Regs.TBCTL.bit.PHSEN = 0x0;              // Disable phase loading
   EPwm9Regs.TBPHS.half.TBPHS = 0x0000;                // Phase is 0
   EPwm9Regs.TBCTR = 0x0000;                           // Clear counter
   EPwm9Regs.TBCTL.bit.HSPCLKDIV = 0x0;            // Clock ratio to SYSCLKOUT
   EPwm9Regs.TBCTL.bit.CLKDIV = 0x0;

   // Setup shadow register load on ZERO
   EPwm9Regs.CMPCTL.bit.SHDWAMODE = 0x0;
   EPwm9Regs.CMPCTL.bit.SHDWBMODE = 0x0;
   EPwm9Regs.CMPCTL.bit.LOADAMODE = 0x0;
   EPwm9Regs.CMPCTL.bit.LOADBMODE = 0x0; 

  // Set Compare values
   EPwm9Regs.CMPA.half.CMPA = EPWM9_CMPA;    // Set compare A value
   EPwm9Regs.CMPB = EPWM9_CMPB;                       // Set Compare B value
  
   // Set Actions
   EPwm9Regs.AQCTLA.bit.PRD = 0x2;                         // Set PWM9A on period
   EPwm9Regs.AQCTLA.bit.CBD = 0x1;                         // Clear PWM9A on event B, down count

   EPwm9Regs.AQCTLB.bit.PRD = 0x1;                        // Clear PWM3A on period
   EPwm9Regs.AQCTLB.bit.CAU = 0x2;                        // Set PWM3A on event A, up count

Thanks,

Mahesh

Mahesh,

Thanks for your kind support!

Will,

I hope these steps will help you going forward.

Manesh,

Thank you for your attention.

I have verified all the configuration code as you specified.  Everything is the same except I'm not using "B" output.  Unfortunately,  I still have no output pin activity from the PWM.

As I mentioned above, all the register settings I am aware of seem to be correct, and I can observe (with the debugger in real-time mode) that the PWM counter (TBCTR and TBSTS) is counting up and down, the Compare register (CMPA) is being updated by my application, and the Action Qualifier (AQCTLA)is set to 0x60.
I've also re-confirmed the GPIO MUX and DIR settings:  
GPIOG1CTRL.GPBMUX2 = 0xFC340550  (GPIO61, 62, 63 all = 0x3 = PWM)
GPIOG1CTRL.GPBDIR = 0xEE000000  (GPIO61, 62, 63 all = 1 = OUTPUT)

EPWMs 7, 8, and 9 are configured the same.  I have debug-code trying to toggle PWM9 with the "software force" yet the GPIO DAT register and the pin itself never change.

The three most confusing things are:
1) The PWM output works on the BLDC example, which I've similarly modified to work with the Concerto on my board.  This verifies the M3 configuration because both use exactly the same .out file for the M3 core.

2) I can change a different  pin on the same GPIO port (GPIO59, used as digital GPIO output).  This confirms that the GPIO port itself is enabled.

3) Toggling Software Force for A and B (AQCSFRC alternates from 0xA to 0x5)  has no effect on the pin.  It is my understanding that this should override all other PWM settings to force the PWM module's output either high or low.  

Any other ideas?  There must be something disconnecting EPWM output from GPIO, and it must be software because the BLDC example works with all 6 PWM outputs.

Thanks,
-Will 

Will,

when you say BLDC example works with all 6 PWM outputs. you mean PWM A/B channels on EPWMs 7, 8, and 9 correct ?

also what hardware are you using ? control card ?

Regards,

Mahesh

Manesh,

Yes, A and B on PWM 7,8,9.

I am using a board we designed.  Obviously the PWMs were moved to allow other peripherals to be used.

Cheers,

-Will

Manesh,

This is probably not the problem (because PWM7-9 work with the BLDC example), but I've noticed a diecrepency in the Datasheet regarding the EPWM interrupt addresses.  This might indicate that there could be other errors with this peripheral.  

See: http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/t/165350.aspx#602446

Thanks,

-Will

I see that there are some other control blocks for the EPWM between the ActionQualifier block and the PWM final output.  These are Dead-Band, PWM-Chopper, and Trip Zone.  So far, I haven't found any problems in those settings, but I'm looking in to it.

-Will