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F29H850TU: Question on EMIF1 pin mapping in Table 5-3

Ben Muller
Prodigy 10 points

Part Number: F29H850TU

Hi TI team,
 
In Table 5-3 of the F29H850TU datasheet(page 83), EMIF1_D2 and EMIF1_D27 appear to be mapped to the same pin for the 176-pin PTS package. The same also seems to apply to the 144-pin RFS package. Could you please let us know if this is expected, or if there may be a typo in the datasheet?  image.png
  • 0
    TI__Mastermind 24711 points

    Hi Ben,

    Our datasheets are directly automated from the device spec so this is not a typo, though I will double check our other documentation to confirm. Likely this is a limitation of the pinmux for the smaller device packages

    Regards,

    Peter

  • 0 in reply to Peter Luong
    Prodigy 10 points

    Hi Peter,

     

    Thanks for looking into this.

     

    I just want to make sure I understand the implication correctly: if EMIF1_D2 and EMIF1_D27 are indeed assigned to the same physical pin on the 176-pin PTS package (and similarly on the 144-pin RFS package), then those two signals would not be available at the same time on that package.

     

    If that is the case, it seems to suggest that EMIF1 is not fully bonded out on the smaller packages, and that a full 32-bit EMIF bus may therefore not be available on those variants.

     

    Could you please confirm whether this is an intentional package limitation, and if so:
    - whether EMIF1 is only partially supported on these packages,
    - what the maximum supported bus width is,

     

    The reason I ask is that the datasheet table currently appears to expose EMIF1 on these packages, while the duplicated pin assignment seems to indicate a package-level limitation for full x32 use.

     

    Best regards,
    Ben
  • 0 in reply to Ben Muller
    TI__Mastermind 24711 points

    Hi Ben,

    I've reviewed our other documentation and specs and the pin mapping detailed in the datasheet is accurate. To give a little background, the EMIF mapping is taken from our F28P65x family of devices where this was not an issue since GPIO82 is available on the 176 pin package. However, on F29H85x, GPIO82 is only present on 256 BGA hence there will be this pinmuxing issue when trying to utilize both D2 and D27.

    I will confirm with our design team on maximum intended bus width for this package but on my own review, I see there is also a limitation with D16 and D22 (due to other EMIF pinmux pins). This points to a maximum bus width of only 16-bit on these packages (at least for my review of the 176-pin package). And 32-bit on 256BGA. I recall a similar limitation on F2837x with smaller pin packages as well 

    Regards,

    Peter

  • 0 in reply to Peter Luong
    TI__Mastermind 24711 points

    Hi Ben, I'm still awaiting a response from our design team

  • 0 in reply to Peter Luong
    Prodigy 10 points
    Hi Peter, thanks for the update. No worries, I’ll wait for their response.