TMS320F28P650DK: ECAP Signal Monitoring

Hi TI support team,

For clarification, I expected the eCAP interrupt to be triggered on each input pulse with a positive pulse width greater than 100000 clock cycles. However, I only saw the ERROR_EVT2 interrupt triggered once, on the very first input pulse. I have tried disabling and re-enabling signal monitoring, the counter, and timestamp capture inside the ISR. Unfortunately, none of these steps helped. It would be greatly appreciated if you could help me with this issue, as I am very stuck at the moment.

Thanks,

Haobo

Hi Zhang,

Apologies for the delayed response. Can u please try the steps mentioned on page 3652 , section 21.5.13.1 of technical reference manual? The tsctr should be in free run mode . It appears that you have used option: TSCTR is stopped on emulation suspension. You can try setting disable_max_early_err bit to zero to generate error as soon as pulse width is greater than mentioned value.

Thanks,

Divesh

Hi Divesh,

Thank you for your reply! Any help you could offer would be greatly appreciated.

I experimented with the Emulation Mode setting during my early tests. It didn't seem to help. I just confirmed again that setting it to "TSCTR is not affected by emulation suspension" has no effect on the outcome. The following are my updated Sysconfig settings.

It is a good idea to generate the error as soon as the pulse width exceeds the limit. I had a line in the code to set the early max error check right after the board initialization, "ECAP_setupEarlyMaxErrorCheck(ECAP_ARC_BASE, ECAP_MONITORING_UNIT_1, ECAP_PULSE_WIDTH_CROSS_MAX_VALUE);".

It seems the eCAP module latches internally into an "error" state when the signal monitor detects an input pulse width that exceeds the set limit. If that is the case, is there a way to clear the error in the ISR or to reset the module entirely?

Thanks,

Haobo

Hi,

You can try clearing interrupt flags corresponding to monitoring unit using ECCLR register documented on page 3714 of Technical Reference Manual.

Thanks,

Divesh

Hi Divesh,

Thanks for your reply.

The code uses "ECAP_clearInterrupt" to clear the interrupt flag (ERROR_EVT2) within the ISR. I even tried intentionally ignoring the interrupt flags in the routine. In that case, the ISR would be triggered consistently.

It seems to me that the error state is latched internally within the processor when the signal monitor detects a condition. Do you have a sample code that meets my application's needs? The closest sample program I found was "ecap_ex5_signal_monitor" from TI. However, this sample program exhibits the same behaviour when I run it on the eval board.

Thanks,

Haobo

Hi Zhang,

Since interrupt is only generated once , there is something wrong in the interrupt configuration. At the end of the ISR, one needs to acknowledge the group interrupts for more interrupts to propagate. This is done by using function Interrupt_ClearACKGroup() in your code. I am not sure that your code is picking up correct group number (corresponding to the ECAP module you are using). Kindly check group number from table 3-2 given on page 144 of Technical Reference Manual.  Here, group number is represented by row. 

Based on the group number, you can choose enumerator ( INTERRUPT_ACK_GROUPx where x=group number corresponding to ecap module being used).

Also, there is no example other than named as "ecap_ex5_signal_monitor" which will emulate your test scenario. 

Thanks,

Divesh

Hi,

Please try using Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP4) instead of the one used by you. Please note that group number for ECAPx module is 4.

Thanks,

Divesh

Hi Divesh,

Thank you so much for your continued support on this issue!

I am currently using the define "INT_ECAP_ARC_INTERRUPT_ACK_GROUP" from board.h to acknowledge the group interrupt. I also confirmed that "INT_ECAP_ARC_INTERRUPT_ACK_GROUP" is set to "INTERRUPT_ACK_GROUP4" in the header file. Please see below.

I imported the TI project "ecap_ex5_signal_monitor" into CCS and made a single correction to the sample code to initialize the global variables, as shown below.

This TI sample program exhibits the same behaviour I observed in my own code. The ERROR_EVT1 interrupt triggers only once. I don't know whether you have an eval board for F28P65X. If you do, could you please confirm whether you see the same behaviour on your setup?

Thanks,

Haobo

Hi Divesh, it would be greatly appreciated if you could share any updates on this question.

Thanks,

Haobo

Hi,

I am trying to arrange a F28P65x LP. Please expect some delay in response.

Thanks,

Divesh

HI,

I tried to run example named ecap_ex5_signal. I am observed same behavior. The ERROR_EVT1 interrupt triggers only once. Please provide some time for identifying the root cause of this issue.

Thanks,

Divesh

Hi,

In the example, munit1_evt1 error generates a trip signal for EPWM1 module. Hence, the same was confirmed by probing the signal after running the example. This was done by disconnecting jumper from GPIO0 to GPIO16 and probing GPIO0 signal (eEPWM1_A).  The trip 1 signal is routed to EPWM digital compare module through EPWMXBAR. Please note source of trip 1 signal is ECAP1_TRIPOUT.

This is the reason why we are not observing monitoring unit interrupt again. Please reach out if there is query.

Thanks,

Divesh