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TMS320F280039C: TMS320F280039C: Higher priority ePWM interrupt not preempting lower priority ISR (same PIE group)

Part Number: TMS320F280039C

Hi,
I am working on the TMS320F280039C. I observed a behavior related to interrupt priority that I’m not able to understand. I am using two ePWM interrupts from the same PIE group (Group 3):

  • ePWM5 → 10 µs period ISR
  • ePWM6 → 20 µs period ISR

Setup:

  • ePWM5 ISR execution time ≈ 1.1 µs
  • ePWM6 ISR execution time ≈ 11 µs

Expected Behavior:

If the 10 µs interrupt (ePWM5) occurs while the 20 µs ISR (ePWM6) is executing, it should preempt the ePWM6 ISR and execute immediately. Why is ePWM5 not preempting ePWM6 ISR, even though it should have higher priority? 

Code Snippet:

__interrupt void epwm5_timer_isr(void)
{
    GpioDataRegs.GPASET.bit.GPIO8 = 1;
    for( j=0; j<10; j++); 
    GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;

    // Clear EPWM5 interrupt flag
    EPwm5Regs.ETCLR.bit.INT = 1;

    // Acknowledge PIE group 3
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

__interrupt void epwm6_timer_isr(void)
{
    GpioDataRegs.GPASET.bit.GPIO23 = 1;
    for( l=0; l<100; l++); 
    GpioDataRegs.GPACLEAR.bit.GPIO23 = 1;

    // Clear EPWM6 interrupt flag
    EPwm6Regs.ETCLR.bit.INT = 1;

    // Acknowledge PIE group 3
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

  • Hi Bhandavi,

    By nature, ISRs on the C28x once entered will run to completion since the context save operation disables interrupts globally. The priorities in the PIE just determine the order that interrupts are serviced if more than one interrupt is pending. So, the behavior you are seeing is actually expected.

    What you are describing is interrupt nesting. To enable this, follow the steps linked here. Let me know if you have any questions. Note that it's very important to follow the software steps exactly so as not to put the PIE in an unexpected state.

    Best Regards,

    Delaney

  • Hi Delaney Woodward,

    Thanks for the clarification — that really helped.

    Best regards,
    Bhandavi