• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 82 subscribers
  • Views 139 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM13E23019: How to understand the SPI Interrupt -- FIFO is at least 1/16 full - "not empty"

Joe Ji
Expert 4350 points

Part Number: AM13E23019
Other Parts Discussed in Thread: SYSCONFIG

Hi Expert

Customer uses SPI for SoC and MCU communication, when the SPI Interrupt is triggerd, the ISR read out all the data in SPI FIFO and ack. when customer using FIFO is ½ full interrupt, the interrupt can be triggerd and ISR run properly, but when customer using FIFO is at least 1/16 full - "not empty", the interrupt trigger Freq is less than expectation and data cannot be properly read out by ISR. I would like to  understand how "not empty" triggered with this SPI design and how to use it properly?

Thanks and best regards

Joe

  • 0
    TI__Mastermind 25890 points

    Hi Joe,

    I'm assuming you are talking about the RX FIFO? If so, is data being sent by the transmitting device at the same rate for both cases? 

    Which value of RXIFLSEL is being set in each case exactly?

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Expert 4350 points

    Hi Delaney

    Yes, it is SPI RX FIFO, 

    Delaney Woodward said:
    is data being sent by the transmitting device at the same rate for both cases?

    Yes

    value of RXIFLSEL ：customer used sysconfig to configure the SPI RX FIFO level, for 2 different cases:

    FIFO is ½ full: 

    DL_SPI_setFIFOThreshold(APP_SPI_CONTROLLER_INST, DL_SPI_RX_FIFO_LEVEL_1_2_FULL, DL_SPI_TX_FIFO_LEVEL_1_2_EMPTY);
    I jump into the drivelib file, the DL_SPI_RX_FIFO_LEVEL_1_2_FULL value is  0x00000020U

    FIFO is at least 1/16 full - "not empty":

     DL_SPI_setFIFOThreshold(APP_SPI_CONTROLLER_INST, DL_SPI_RX_FIFO_LEVEL_NOT_EMPTY, DL_SPI_TX_FIFO_LEVEL_1_2_EMPTY);
    I jump into the drivelib file, the DL_SPI_RX_FIFO_LEVEL_NOT_EMPTY value is  0x00000040U
    One thing confusing me is that if I assume not empty should be triggered when there is the data in FIFO, looks like the interrupt will not be able to be cleared once the RX FIFO has some data in it, and in customer test the interrupt also cannot run normally.
    Thanks
    Joe
  • 0 in reply to Joe Ji
    TI__Mastermind 25890 points

    Hi Joe,

    I see, yes that’s the behavior I would expect as well. Let me test this on my end and get back to you next week.

    Best Regards,

    Delaney

  • +1 in reply to Delaney Woodward
    TI__Mastermind 25890 points

    Hi Joe,

    Apologies for the delay. 

    I ran some tests myself with the RX FIFO "not empty" interrupt setting. My test transmits10 data bytes and reads one received byte at a time. I see that the ISR is triggered 10 times and all data is received correctly. 

    How many bytes is the customer reading inside their ISR? 

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Expert 4350 points

    Hi Delaney

    I think there is some setting issue in customer side, cannot recreate in my side too, let's close this thread.

    Thanks

    Joe