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TMS320F28386D: Simultaneous access interference on IPC registers

Clément Letonnelier
Expert 2986 points

Part Number: TMS320F28386D

Hello,

Can you confirm that there is simultaneous access:

  • By CPU1 in write to CPU1TOCPU2IPCSENDDATA
  • By CPU2 in read to CPU1TOCPU2IPCRECVDATA 

None of them will be delayed as these are pure registers, in contrary to when accessing peripheral frames for example.

Best regards,

Clément

  • +1
    TI__Expert 3105 points

    Hi Clement,

    Yes, CPU1 writing to CPU1TOCPU2IPCSENDDATA and CPU2 reading from CPU1TOCPU2IPCRECVDATA can occur simultaneously without either CPU being delayed. This is because the IPC module architecture shows that these are dedicated register spaces with separate access paths for each CPU:

    • CPU1 has R/W access to CPU1TOCPU2IPCSENDDATA
    • CPU2 has read-only access to CPU1TOCPU2IPCRECVDATA

    Hope this helps answer your question.

    Thanks,

    Ira