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Original question:

TMS320F28388D: Problem using "IPC message copy to RAM boot" to start CM

TMS320F28388D: TMS320F28388D IPC Message Copy to RAM Boot Mode

Tyler Shaw
Prodigy 10 points

Part Number: TMS320F28388D

I am having trouble with booting the CM through IPC Message Copy to RAM Boot Mode.

 

I made a basic test program that runs on the CM to set the vector table offset to the RAM vector table and then an inifinite while loop. The program works through the CCS debugger but not when I try to load it through CPU1's IPC MSGRAM.

 

I have reserved an 8 byte region at the beginning of non reserved S0 RAM (0x20000800-20000807) for the RESETISR, which is the boot to RAM entry point used in startup_cm.c. The rest of the bootloader follows and is limited to 2000 bytes (1000 words).

 

I used similar procedure to reserve memory, write to IPC MSGRAM, and boot for CPU2 and got that working correctly with a more complicated program. However, I am having issues with the CM and it seems to be stuck in a hard fault whenever I try to load the bootloader into IPC MSGRAM. I can see the same contents on both the CPU1 and CM's MSGRAM1, but I don't see anything in the CM's S0 RAM (it's just all 0's).

 

Is there a special format or header needed for this boot mode? Should I be including the RESETISR in the boot image? Is there anything else I am missing?

 

Thank you.

  • 0
    TI__Expert 4095 points

    Hi Tyler,

    Check the CM Boot Status Register at address 0x2000 0000 (also mirrored in CMTOCPU1IPCBOOTSTS). The bit fields will tell you exactly what's failing:

    Bit
    Meaning
    31
    Boot ROM finished running
    23
    Hard Fault occurred
    19
    Invalid length in CPU1TOCMIPCBOOTMODE
    18
    Invalid/missing configuration in CPU1TOCMIPCBOOTMODE
    7:0
    Current boot state (0x4 = running IPC copy, 0x8 = waiting for CPU1TOCMIPCFLG0)

    Key Requirements You May Be Missing

    1. CPU1TOCMIPCBOOTMODE Register Format

    The register must be configured as follows:

    • Bits 31:24 (Key): Must be 0x5A
    • Bits 19:16 (Copy Length): 0x1 to 0xA (100 to 1000 words). For your 1000-word bootloader, use 0xA
    • Bits 15:8 (CM Frequency): CM clock in MHz (e.g., 0x7D for 125 MHz)
    • Bits 7:0 (Boot Mode): Must be 0x0C for IPC Message RAM copy to S0RAM

    2. Vector Table Structure at 0x20000800

    This is critical and differs from CPU2. The CM is a Cortex-M core, so at address 0x20000800 it expects a proper ARM vector table — not just the ResetISR function code:

    • Word 0 (0x20000800): Initial Stack Pointer value
    • Word 1 (0x20000804): Reset Handler address (your entry point)

    You mentioned reserving 8 bytes for the RESETISR. You need to ensure those 8 bytes contain the vector table entries (SP + Reset address), not the function body itself.

    3. Thumb Mode Bit (LSB Must Be Set)

    For Cortex-M cores, all function pointers and branch targets must have bit 0 set to 1 to indicate Thumb mode. If your Reset Handler address in the vector table is 0x20000808, it must be stored as 0x20000809. Failure to set this bit causes an immediate hard fault.

    4. Byte Packing from C28x to CM

    Since C28x has no native 8-bit type (uint8_t is actually 16 bits), you must pack two bytes into each 16-bit word when writing to IPC MSGRAM:

    for(int i = 0; i < raw_bytes_len; i += 2) {
    packed_bytes[i/2] = raw_byte[i] + (256 * raw_byte[i+1]);
    }

    Failure to pack correctly results in corrupted data in Message RAM and causes the CM to hard fault.

    Recommended Debug Steps

    1. Read the boot status register at 0x2000 0000 to confirm whether the copy is even being attempted
    2. Verify your CPU1TOCMIPCBOOTMODE register has key=0x5A, mode=0x0C, and a valid length
    3. Ensure CPU1 sets CPU1TOCMIPCFLG0 to allow the CM to start booting
    4. Confirm your vector table at 0x20000800 has a valid SP and a Thumb-mode Reset address (LSB=1)
    5. Verify byte packing when writing from CPU1 to MSGRAM

    Thanks,

    Ira

  • 0 in reply to Ira Thete
    Prodigy 10 points

    Hi Ira,

    Thank you for your response. I was able to get my CPU1 to boot up the CM.

    For anyone wondering what the issue was, it was that you need the Vector Table Structure mentioned above. Also, you cannot use a for loop to directly copy into IPC MSGRAM, but you have to declare a section in memory that is linked to CPU1's CPU1CMIPCMSGRAM1. The C array must be placed directly in this section. See the example code flash_kernel_c28x_cm_ex1 for more details.