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TMS320F28375D: Abnormal duty cycle

Chi Zhang2
Intellectual 2980 points

Part Number: TMS320F28375D

Hi Expert, 

My customer face 2 issues in F28375D. so here want your more advice. Only EPWM8A reproduce this issue, but EPWM8B is good. 

Case 1: When the photovoltaic Boost circuit operates at the working condition of low input voltage and high output voltage, the actual duty cycle of the corresponding EPWM output suddenly jumps to full duty cycle, far exceeding the theoretical duty cycle value, which directly triggers the overcurrent protection of the Boost circuit. All other hardware and software conditions remain unchanged. After merely replacing the DSP28375 with a new one and flashing the exactly same firmware program, the abnormal full-duty-cycle phenomenon disappears completely.

Case 2: During the thermal shock test of the complete inverter, under the Boost operating condition of low input voltage and high output voltage, abnormal full duty cycle of Boost EPWM occurs at two time nodes:
1. Shortly before EPWM wave shutdown upon approaching the over-temperature protection threshold;
2. When the temperature drops below the over-temperature protection threshold and EPWM duty cycle is re-enabled.

This anomaly also causes Boost overcurrent protection, and the problem is eliminated after replacing the DSP chip with a new unit as well.

BR

Chi

  • 0
    TI__Intellectual 2980 points

    More test input: 

    1. After change the EPWM from 200MHz to 100MHz, EPWM8A will work well but EPWM9 failed. 
    2. check PLL setting, it is below 400MHz
    3. By monitoring the EPWM TBCTR register during the abnormal occurrence, we found that the TBCTR value of EPWM9 has a significant offset compared with other EPWM modules. This abnormal operating condition occurs randomly. The synchronous mechanism is not enabled currently.

      Are there any specific configuration conditions that can cause TBCTR counter offset?

      The reading difference of TBCTR values among other modules is 4, which corresponds to the execution time interval of two consecutive register read instructions and is regarded as normal behavior.
      The normal TBCTR value of EPWM9 should be 1169, while the actual value is only 99, resulting in an equivalent phase offset of approximately 14.3μs. This leads to a large internal phase shift on the low-voltage side, whereas the clock of other EPWM modules remains synchronized with each other.

    BR

    Chi

  • 0 in reply to Chi Zhang2
    TI__Expert 5445 points

    Hi Chi

    I am working on it. Please allow 1-2 days to respond to the issue. 

    Thank you

    Amir Hussain

  • 0 in reply to Amir Hussain
    TI__Expert 5445 points

    Hi Chi

    Could you please share below?

    1. the EPWM configuration?

    2. the circuit diagram mentioning which switch is operated using EPWM8 and EPWM 9.

    3. Control method

    4. EPWM waveform when the abnormal condition occurs.

    5. After changing the MCU, does the issue re-occur. If yes, how often?

    6. Is the protection CBC or OST?

    Thank you 

    Amir Hussain

  • 0 in reply to Amir Hussain
    TI__Intellectual 2980 points

    Hi Amir

    please check customer feedback

    our core question in practical application is: what configurations can cause counting offset of the EPWM9 TBCTR register.


    We previously encountered an issue where the EPWM8A drive duty cycle abnormally saturated to 100%. Our PLL configuration refers to the code below, and the configured frequency does not exceed 400MHz.

    Currently, our EPWM clock frequency is set to 200MHz. After we reduced the clock frequency of all EPWM modules to 100MHz, the abnormal full-duty issue of EPWM8A no longer occurred. However, anomalies appeared on the EPWM9 module.

    During fault monitoring of the EPWM TBCTR register, we found that the TBCTR value of EPWM9 had a significant offset compared with other EPWM modules. This issue occurs probabilistically, and no synchronization mechanism is enabled currently. We would like to confirm: what configuration scenarios will lead to TBCTR counting offset?

    For other EPWM modules, the read difference of TBCTR values is 4 cycles, which matches the instruction interval between two adjacent register read operations and is regarded as normal behavior. For EPWM9, the expected normal TBCTR value is 1169, while the actual measured value is only 99, resulting in an equivalent phase offset of approximately 14.3μs. This further manifests as severe internal phase shift on the low-voltage side. The clocks of all other EPWM modules remain synchronized with each other.

  • 0 in reply to Chi Zhang2
    TI__Expert 5445 points

    what configurations can cause counting offset of the EPWM9 TBCTR register.

    The phase shift configuration can cause counting offset. If phase shift for EPWM9 counter is enabled, its counter value may change on the sync event. If sync for EPWM9 is enabled, you should have it configured in the code like 

     EPWM_enablePhaseShiftLoad(EPWM9).

    For the shift, EPWM 9 will have a syncin signal enabled that comes from another EPWM module. The phase shift/offset occurs when synin signal is received from amother PWM. The value of phase shift depends on the configured value based on 

    PWM_setPhaseShift(EPWM9, phase shift);

    From the counter value data you shared, it looks like all EPWMs are in sync with 0 phase shift except the EPWM9.     Can you share the configuration of the EPWMs?

    Thank you 

    Amir Hussain