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F29H859TU-Q1: Why it isn't clear interrupt flag in timer interrupt?

Shuqing Zhou
Expert 3525 points

Part Number: F29H859TU-Q1

Hi team,

I ask this for my customer.

In our TRM, it says the recommended interrupt handling process, and shows it should clear the interrupt flag before it returns from the ISR

image.png

And in our PWM, ADC and other peripheral interrupt demo, it should clear INT flag before it exits the ISR

image.png

but it isn't clear the timer interrupt flag

image.png

could you help to explain it? thanks

BRs

Shuqing

  • 0
    TI__Mastermind 34673 points

    Hi Shuqing,

    The CPU Timer on the F29H859TU-Q1 uses a hardware auto-clear mechanism — the timer overflow flag is automatically cleared when the interrupt is acknowledged by the interrupt controller upon entering the ISR. This is why the timer demo code doesn't include explicit flag-clearing code, unlike PWM, ADC, and other peripheral demos [1].

    This is a hardware design difference, not an oversight in the demo code.

    Why Timer Behaves Differently from PWM/ADC

    Peripheral
    Flag Clearing
    Reason
    CPU Timer
    Automatic (hardware)
    Overflow flag auto-clears on interrupt acknowledgment
    PWM (ePWM)
    Manual (software)
    Trip/event flags persist until explicitly cleared via TZCLR register [2]
    ADC
    Manual (software)
    Event flags require software to set a clear bit; hardware has priority if both occur simultaneously [3]
    LIN
    Manual (software)
    Must clear SCIFLR flag, verify it's cleared, then clear global interrupt [4]

    For peripherals like ADC, the flags are latched — they remain set until software explicitly clears them. If you don't clear them, no further interrupts of that type will be generated [3]. The CPU Timer, by contrast, handles this automatically in hardware, simplifying the ISR implementation.

    That said, the DriverLib does provide CPUTimer_clearOverflowFlag() if manual clearing is ever needed [1]. And the general C29x interrupt coder template still includes the comment // Ensure to clear all interrupt flags as a reminder for peripherals that require it [5].

    For production code, it is still good practice to follow the TRM's recommended interrupt handling sequence. While the CPU Timer auto-clears its flag, explicitly calling CPUTimer_clearOverflowFlag() adds no harm and makes the code self-documenting and consistent with other peripheral ISRs.

    To help refine this recommendation, it would be helpful to know:

    • Whether the customer is using CPU Timer 0, 1, or 2 (behavior should be consistent, but worth confirming)
    • Whether the customer is experiencing any functional issues (spurious interrupts, missed interrupts) or is simply seeking clarification on the documentation inconsistency

    Resources:

    1. F29H85x CPU Timer API Documentation
    2. F29H85x TRM - ePWM Trip Zone and Cycle-by-Cycle Behavior
    3. F29H85x TRM - ADC Event Status Register
    4. F29H85x TRM - Servicing LIN Interrupts
    5. C2000 IDEA Interrupt Coder Application Note

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    TI__Expert 3525 points

    Hi Zackary,

    Could you help to point out where have the statement you mentioned in TRM?

    BRs

    Shuqing

  • 0 in reply to Shuqing Zhou
    TI__Mastermind 34673 points

    Hi Shuqing,

    The relevant TRM statement is found in the TCR (Timer Control Register) field descriptions for the CPU Timer module. Specifically, the TIF (Timer Overflow Flag) bit description in Table 2-578 of the F29H85x TRM states:

    "TIF is not cleared automatically and does not need to be cleared to enable the next timer interrupt." [1]

    Correction to the Previous Response

    I need to clarify something important from the previous reply. The TRM does not describe a "hardware auto-clear" mechanism in the way it was stated. Rather, the actual behavior documented in the TRM is:

    Aspect
    What the TRM Says
    Auto-clear?
    No — "TIF is not cleared automatically" [1]
    Required for next interrupt?
    No — "does not need to be cleared to enable the next timer interrupt" [1]
    How to clear manually
    Write a 1 to the TIF bit (R/W1C type) [1]

    So the reason the timer demo code doesn't clear the interrupt flag is not because it auto-clears, but because clearing it is simply not required for the timer to generate subsequent interrupts. The flag is a status indicator that persists until you explicitly clear it, but unlike PWM/ADC flags, leaving it set does not block future timer interrupts [1].

    This is the key hardware design difference: for peripherals like ePWM and ADC, the interrupt flag must be cleared or the peripheral will not generate another interrupt. For the CPU Timer, the interrupt mechanism operates independently of the TIF flag status.

    TRM Location

    You can find this in the CPU Timer chapter, specifically:

    • Table 2-578: TCR Register Field Descriptions — Bit 15 (TIF) [1]
    • Page 899 of the F29H85x TRM (spruj79a)

    The DriverLib function CPUTimer_clearOverflowFlag() is available if the customer wants to clear TIF for status-tracking purposes, but it is functionally optional for interrupt generation.

    To help refine this further, it would be helpful to know:

    • Whether the customer is experiencing any functional issues (missed or spurious interrupts), or is this purely a documentation clarification question
    • Which CPU Timer instance (0, 1, or 2) is being used
    1. F29H85x TRM - TCR Register Field Descriptions (Table 2-578)

    Best Regards,

    Zackary Fleenor