F28E120SC: Pparallel GPIO bootloader error

Hello,

I don't have a parallel boot host programmer readily available for me to test with, but I will reach out internally to confirm how parallel boot on F28E12x was verified.

Can you follow step 2 of the previous thread and observe the state of the device when it hangs?

Emulate parallel boot (using the EMU boot registers) and see if the issue occurs. If it does, load the Boot ROM symbols and observe where the ROM bootloader is getting stuck. Please refer to SPRUJH3 for details. In particular:

• Section 2.2 Emulation Boot
• Section 5.3 No Symbols Defined When Debugging Boot ROM

Best,

Matt

Hi Matt,

sorry, but we do not have an additional time(and people) for investigating the root of problem with parallel boot loading. As I wrote before -

we use the same algorithm for earlier TMS320 series, no problem with loading. You wrote that F28E120SC have to be the same design - requirement for maintaining the compatibility.

So I will wait for your investigation to see if the problem occurs on your side too. Please do not close this thread.

Best regards,

Tomas

Hello,

Tomas Lehotsky said:

In the captured data you can see that I try to store ten words(0x0A) of data 0000 0003 C84D 0000 0010 FFF0 0000 0003 0001 0000 to address 0x128 - M0RAM.

I just realized this, but address 0x128 is part of the Boot ROM's reserved memory. Please do not write to this region when using parallel boot mode.

Best,
Matt

Hi Matt,

regarding the reserved BootROM memory - I have used the default linker file from examples at TI C2000Ware_26_00_00_00 directory. So I correct this file:

   BEGIN            : origin = 0x000000, length = 0x000002
   BOOT_RSVD        : origin = 0x000002, length = 0x0001BE     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001C0, length = 0x000240

But this change do not solve my problem.

For parallel boot mode we are using:

D0 - D7: GPIO0, GPIO1, GPIO3, GPIO4, GPIO5, GPIO24, GPIO28, GPIO29

DSP Control pin: GPIO224

Host Control pin: GPIO242

The F28E120SC is blank new device ordered from TI.

As we wrote before, the problem cause after some words, when DSP control pin is not tied to L - the device indicate, that is ready for receiving another word.

I'm attaching captured data from parallel loading - F28E120_parallel_capture_fail.logicdata

For compare I also attach the good working parallel loading for TMS320F280037 device - TMS320F280037_OK_parallel.logicdata

The F28E120S one word loading lasts for around 32ms: 

On other hand, for TMS320F280037 one word loading lasts for around 25us:

The difference between TMS320F280037 and F28E120 is suspicious! It lasts so long time and I suppose this is the root of problem. Something is wrong.

Can you confirm that we are using correct parallel pins for loading?

Best regards,

Tomas

F28E120_parallel_capture_fail.zipTMS320F280037_OK_parallel.zip

Hello,

Apologies, I am out of office until next Wednesday. Please expect a delay in response until then.

Best,

Matt

Hello,

I can confirm those are the correct pins for parallel bootloading. 

Tomas Lehotsky said:

But this change do not solve my problem.

To confirm my understanding: F28E12x is able to program the RAM now that the ROM reserved section was extended correctly, but it is done at a much slower rate compared to F28003x? 

I'm working with our internal teams to root cause this. There are different internal oscillators on F28E12x compared to previous C2000 devices.

Best,
Matt

Hi Matt,

no, the loading data to RAM using parallel boot is still not working - the process of loading is always interrupted after a few words is load... You can check it in the captured data in my previous post.

Best,

Tomas

Hi Tomas,

Thank you for clarifying that for me. I'll be meeting with the Boot ROM team early next week, hopefully I can have an answer for you asap.

Best,

Matt

Hi,

any news in this case?

Hi, 

My meeting got moved to Thursday due to a product deadline, hopefully I will have an answer by then. All I have confirmed is that the parallel boot code is exactly reuse between F28P55x and F28E12x devices. From a Boot ROM and SW perspective we didn’t have any change specific to F28E12x that can result in slower performance.

Best,
Matt

Hello,

To keep you updated, I've received our internal parallel boot test code and will attempt to replicate your issue. I will have an update by early next week.

Best,
Matt

Hi Matt,

any updates?

Hi Tomas,

I'm observing no abnormalities on my end. I'm using alternate parallel boot (BOOTDEF = 0x20). The DSP write time is about 37us, which is comparable to other C2000 devices. I also have no issues writing several words starting from address 0x1C0. 

Best,
Matt

Hi Matt,

is there any reason why don't you use the default parallel boot (BOOTDEF = 0x00)? Can you verify also default parallel boot option?

The default boot mode selection pins is GPIO24 and GPIO32. I have this pins tied to L before reset pin is asserted to H. For BOOTDEF = 0x00 the GPIO24 is also one of the D0-D7 GPIO pins...

I assume, that you are using some evaluation board for the tests. Do you have connected some crystal/resonators/external clock to the F28E120? Can you provide the scheme?

Best regards,

Tomas 

Hello,

I used the F28E12x LaunchPad, which only brings out the GPIOs for alternate parallel boot. Operation should be the same between boot modes.

Tomas Lehotsky said:

Do you have connected some crystal/resonators/external clock to the F28E120? Can you provide the scheme?

On reset, the Boot ROM is clocked from the internal oscillator, regardless of external clocks being connected. Their presence/absence won't impact the ROM bootloaders execution.

The board's design files are provided here: https://www.ti.com/tool/LAUNCHXL-F28E12X#design-files

Tomas Lehotsky said:

The default boot mode selection pins is GPIO24 and GPIO32. I have this pins tied to L before reset pin is asserted to H. For BOOTDEF = 0x00 the GPIO24 is also one of the D0-D7 GPIO pins..

This shouldn't impact the bootloader functionality. As long as the hold time for boot-mode pins (1.5ms) is not violated, parallel boot will be executed and will be able to use GPIO24.

Source: F28E12x Datasheet

Best,
Matt