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Original question:

TMS320F2800137: DAC Output using CMPSS module

TMS320F280049C: Query Regarding 500-Count Offset in CMPSS-Based ePWM Trip Configuration

Ankita Dhiman
Prodigy 10 points

Part Number: TMS320F280049C

I am configuring the ePWM trip in my code using the CMPSS module.

I have configured the required modules for this trip path:

  • CMPSS module
  • ePWM X-BAR
  • ePWM Digital Compare and Trip Zone registers

The trip is configured based on the CMPSS DACHVAL reference value. But I am seeing a constant offset between the configured DAC reference and the ADC raw value at which the trip actually happens.

DACHVAL is 1000 then the adc raw value at the trip is -> 500

DACHVAL is 2000 then the adc raw value at the trip is -> 1500. 

DACHVAL is 3000 then the adc raw value at the trip is -> 2500. 

I have also verified the CMPSS, ePWM X-BAR, and ePWM trip register configurations, but the issue is still present.

Im sharing the code for the configuration. 

what is the reason for that? 

        // testing
        AnalogSubsysRegs.CMPHPMXSEL.bit.CMP2HPMXSEL     = 1;            // for ADC C1
        Cmpss2Regs.COMPCTL.bit.COMPDACE                 = 1U;           // Enable CMPSS module
        Cmpss2Regs.COMPCTL.bit.COMPHSOURCE              = 0U;           // High comparator negative input = DAC |Positive input = external CMPSS analog input
        Cmpss2Regs.COMPCTL.bit.COMPHINV                 = 0U;           // Do not invert high comparator output
        Cmpss2Regs.COMPCTL.bit.CTRIPHSEL                = 0U;           // Select asynchronous comparator output for CTRIPH |This gives fastest trip response
        Cmpss2Regs.COMPCTL.bit.CTRIPOUTHSEL             = 0U;           // Select asynchronous comparator output for CTRIPOUTH
        Cmpss2Regs.COMPDACCTL.bit.SELREF                = 0U;           // DAC reference = VDDA
        Cmpss2Regs.COMPDACCTL.bit.DACSOURCE             = 0U;           // DAC value source = shadow register
        Cmpss2Regs.COMPDACCTL.bit.SWLOADSEL             = 0U;           // DAC load on SYSCLK
        Cmpss2Regs.DACHVALS.bit.DACVAL                  = 3000U;          // Set DAC high threshold = mid ADC value
        Cmpss2Regs.DACHVALA.bit.DACVAL                  = 3000U;
        Cmpss2Regs.COMPSTSCLR.bit.HLATCHCLR             = 1U;           // Clear CMPSS high comparator latch if used earlier
        Cmpss2Regs.COMPCTL.bit.COMPLSOURCE      = 0;        // inverting out of comp driven by dac5
        Cmpss2Regs.DACLVALS.bit.DACVAL          = 0;        // not using lower dac   

    EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 = 0U;        // Route CMPSS1 CTRIPH to EPWM XBAR TRIP4
        EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 = 1U;          // Enable MUX0 for TRIP4

        EPwm4Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3U;
        EPwm4Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;     // Generate event when DCAH is high
        EPwm4Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;      // Use original/unfiltered DCAEVT1 signal
        EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Asynchronous trip path
        EPwm4Regs.TZSEL.bit.DCAEVT1 = 1U;               // Enable DCAEVT1 as one trip source

        EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
        EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO;

        // Clear old trip flags
        EPwm4Regs.TZCLR.bit.DCAEVT1 = 1U;
        EPwm4Regs.TZCLR.bit.OST     = 1U;
        EPwm4Regs.TZCLR.bit.INT     = 1U;

 

  • 0
    TI__Mastermind 34643 points

    Hello Ankita,

    Thank you for the detailed information. The 500-count offset you're observing between your CMPSS DACHVAL setting and the ADC raw value at trip is expected behavior, not a configuration error.

    The root cause is that the CMPSS DAC and ADC modules use different reference voltage configurations, which results in different scaling factors for their digital codes.

    Here's what's happening:

    The CMPSS DAC has a 12-bit resolution (0-4095 counts) and uses VDDA as the reference. The ADC also has 12-bit resolution but may be configured with a different reference voltage or input scaling. When you set DACHVAL to a specific count, the CMPSS generates an analog voltage. However, when the ADC samples that same analog voltage, it converts it back to a digital code using its own reference, which can result in a different count value.

    The consistent 500-count offset across all your test points (1000→500, 2000→1500, 3000→2500) indicates a systematic scaling difference between the two modules.

    To resolve this, you have two options:

    1. Apply a software correction factor to your DACHVAL setting to account for the offset:

      #define DAC_OFFSET 500
uint16_t desired_adc_trip = 2500;
Cmpss2Regs.DACHVALS.bit.DACVAL = desired_adc_trip + DAC_OFFSET;
Cmpss2Regs.DACHVALA.bit.DACVAL = desired_adc_trip + DAC_OFFSET;

    2. Verify your ADC reference configuration matches your CMPSS DAC reference. Check that both are using VDDA and that the ADC input range matches the CMPSS output range.

    Additionally, please verify:

    • Your ADC reference voltage configuration (internal or external reference)
    • The voltage range setting for the ADC channel connected to ADCC1
    • Whether any signal conditioning or scaling is applied between the CMPSS and ADC inputs

    Your CMPSS and ePWM trip configuration looks correct. The issue is purely a scaling mismatch between the DAC output interpretation and ADC input interpretation.

    Let me know if you need help determining the correct scaling factor or if the offset persists after applying the correction.

    Best Regards,
    Zackary Fleenor

  • 0
    TI__Mastermind 34643 points

    Hello Ankita,

    I wanted to follow up on the CMPSS DAC offset issue we discussed last week. Have you had a chance to investigate the reference voltage configurations between your CMPSS DAC and ADC modules?

    To help move this forward, could you please provide:

    1. ADC Configuration Details:

      • What reference voltage is your ADC using (VDDA, VREFHI, internal, or external)?
      • What is the ADC input voltage range configuration for the ADCC1 channel?
      • Can you share the relevant ADC configuration code (similar to what you shared for CMPSS)?

    2. Voltage Measurements:

      • If possible, can you probe the analog voltage at the CMPSS2 input pin when the trip occurs?
      • This will help us verify whether the 500-count offset is due to reference scaling or an actual voltage difference.

    3. Clarification:

      • Are you comparing the CMPSS DACHVAL directly against an ADC reading of the same analog signal, or are these two separate signals?
      • Is the ADC sampling the CMPSS input pin or a different node in your circuit?

    The consistent 500-count offset strongly suggests a reference voltage mismatch between the two modules. Once we understand your ADC configuration, we can calculate the exact correction factor you'll need.

    If you've already resolved this or moved in a different direction, please let me know so I can close out the thread appropriately.

    Looking forward to your response.

    Best Regards,
    Zackary Fleenor