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TMS320F28P650DK: what's the HRERROR flags in ECAP ECCTL2.CTRFILTRESET description?

Chsang Barry
Prodigy 80 points

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: C2000WARE

hi, experts!

may you have a nice day!

In the description of the ECCTL2 register table for eCAP, writing 1 to the CTRFILTRESET bit can clear the HRERROR flag. However, I did not find this bit in the TRM document. Could you please tell me what this bit is?

Looking forward to your reply. 

Best regards! 

  • 0
    TI__Mastermind 33833 points

    Hi Chsang,

    Thank you for the kind words — hope you're having a great day too!

    Good news: the CTRFILTRESET bit does exist in the TRM for your TMS320F28P650DK. It's bit 11 of the ECCTL2 register. Let me explain exactly what it is and where to find it.

    CTRFILTRESET is a write-1-to-clear (W1C) reset bit at bit position 11 in the ECCTL2 register [1]. Writing a 1 to this bit resets all of the following:
    • The event filter
    • The counter and modulo counter
    • The CEVT[1,2,3,4] flags
    • The CNTOVF flag
    • The HRERROR flags

    Reading this bit always returns 0 and has no effect [1].

    This bit lets you start the eCAP module from a known, clean state — particularly useful if spurious inputs were captured while you were configuring the module. It's designed for initialization and debug scenarios [2].

    Note: CTRFILTRESET does not affect signal monitoring interrupts — those are unaffected by this reset [2].

    CTRFILTRESET is a Type 1 eCAP enhancement that was added on top of the older Type 0 eCAP [2]. Your TMS320F28P650DK uses Type 3 eCAP modules, which inherit all Type 1 features including this bit [3]. You can also see CTRFILTRESET referenced in:

    • The eCAP block diagram as a control input to the interrupt/flag control logic [4]
    • The Continuous/One-shot block diagram, where it connects to the modulo counter reset [5]
    • The Event Prescaler section, which notes the prescaler can be reset via this bit [6]

    It's worth noting that we have acknowledged documentation gaps in the TMS320F28P650DK TRM — some register tables and bitfield descriptions were inadvertently omitted or are incomplete [7]. If you're looking at an older revision, the CTRFILTRESET description may not appear clearly. The definitive register-level reference can also be found in the ecap.h header file in C2000Ware [7], which contains the complete register structure.

    To help refine this further, it would be useful to know:

    • Which specific TRM revision/section you were reviewing where this bit appeared to be missing — this would help confirm whether it's a documentation version issue
    • Whether you're working with HRCAP-enabled eCAP instances (eCAP-6 or eCAP-7), where HRERROR is most relevant
    1. TMS320F28P65x TRM — ECCTL2 Register (Table 21-14)
    2. TMS320F28P65x TRM — eCAP Features (Section 21.1.1)
    3. eCAP Module Type Description (Table 3-41)
    4. TMS320F28P65x Datasheet — eCAP Features
    5. TMS320F28P65x TRM — Continuous/One-shot Block Diagram
    6. TMS320F28P65x TRM — Event Prescaler (Section 21.5.1)
    7. TI E2E — TMS320F28P650DK eCAP Documentation Gap

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 80 points

    Thank you for your response, but you misunderstood the question. I would like to know what the "HRERROR" flag means and where it is documented.

  • +1 in reply to Chsang Barry
    TI__Mastermind 33833 points

    Hi Chsang,

    Apologies for the misunderstanding here.

    This is a documentation issue in the chapter, and I will file an internal ticket to track the update efforts.

    HRERROR is actually an ECAP interrupt option used for internal testing that should not be included in this register description.

    Raw Description:

    HRERROR is set if pulse width of input signals is detected to be < 3*HRCLK cycles. Due to synchronizer uncertainty, it is not possible to measure pulse width accurately. This logic does work of all cases, for example input pulse less than a cycle may not event get detected by synchronizer, a pulse width 2*HRCLK cycles may be seen as 3*HRCLK cycle on synchronizer output hence may go undetected. This logic is not reliable but may be useful for internal testing.

    Please do not worry about this flag for your usage. The actual interrupt option is correctly removed from the registers, which is why you don't find it anywhere.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 80 points

    thank you very much, Zackary !