Part Number: TMS320F28P650DH
Hi Experts,
My customer is using the CMPSS6 to trip ePWM11 and ePWM12, the tripe route is:
CMPSS6->ePWM xbar trip3->DCEVTA -> TZ.
Althourgh ePWM11 and 12 share the same source, they are not tripped at the same moment, below is the screen shot.
As you can see, the blue is tripped before yellow.
Blue is ePWM12 and yellow is ePWM11.
Below is the configurations:
//--- CMPSS6 I_dischg3 ----
EALLOW;
Cmpss6Regs.COMPCTL.bit.COMPDACE = COMPD_ENABLE; //Enable CMPSS
Cmpss6Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC; //NEG signal comes from DAC for high comparator
Cmpss6Regs.COMPCTL.bit.COMPLSOURCE = NEGIN_DAC; //NEG signal comes from DAC for low comparator
Cmpss6Regs.COMPDACHCTL.bit.SELREF = CMPSS_REFERENCE_VDDA; //Use VDDA as the reference for DAC
Cmpss6Regs.DACHVALS.bit.DACVAL = DISCHG_CMPH_VALUE;
Cmpss6Regs.COMPCTL.bit.COMPHINV = 0; //0; //disable output invert
Cmpss6Regs.DACLVALS.bit.DACVAL = CHG_CMPL_VALUE;
Cmpss6Regs.COMPCTL.bit.COMPLINV = 1; //enable output invert
// Configure Digital Filter
Cmpss6Regs.CTRIPHFILCLKCTL = 0x02; //Maximum CLKPRESCALE value provides the most time between samples
Cmpss6Regs.CTRIPHFILCTL.bit.SAMPWIN = 0x0B; //Maximum SAMPWIN value provides largest number of samples
Cmpss6Regs.CTRIPHFILCTL.bit.THRESH = 0x0B; //Maximum THRESH value requires static value for entire window
Cmpss6Regs.CTRIPHFILCTL.bit.FILINIT = 1; //Reset filter logic & start filtering
Cmpss6Regs.CTRIPLFILCLKCTL = 0x02; //Maximum CLKPRESCALE value provides the most time between samples
Cmpss6Regs.CTRIPLFILCTL.bit.SAMPWIN = 0x0B; //Maximum SAMPWIN value provides largest number of samples
Cmpss6Regs.CTRIPLFILCTL.bit.THRESH = 0x0B; //Maximum THRESH value requires static value for entire window
Cmpss6Regs.CTRIPLFILCTL.bit.FILINIT = 1; //Reset filter logic & start filtering
// Configure CTRIPOUT path
//Digital filter output feeds CTRIPH and CTRIPOUTH
Cmpss6Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;
Cmpss6Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_ASYNCH;
Cmpss6Regs.COMPCTL.bit.CTRIPLSEL = CTRIP_ASYNCH;
Cmpss6Regs.COMPCTL.bit.CTRIPOUTLSEL = CTRIP_ASYNCH;
Cmpss6Regs.COMPHYSCTL.bit.COMPHYS = COMPHYS_VALUE;
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP6HPMXSEL = 1 ;// ADCC0 IN CMP6HP1
AnalogSubsysRegs.CMPLPMXSEL.bit.CMP6LPMXSEL = 1 ;// ADCC0 IN CMP6HL1
EPwmXbarARegs.OUT3MUX0TO15CFG.bit.MUX10 = 0; //Configure TRIP3 to be CTRIP6H or CTRIP6L
EPwmXbarARegs.OUT3MUXENABLE.bit.MUX10 = 1; //Enable TRIP3 Mux for Output
EPwmXbarARegs.OUT3MUX0TO15CFG.bit.MUX11 = 0; //Configure TRIP3 to be CTRIP6H or CTRIP6L
EPwmXbarARegs.OUT3MUXENABLE.bit.MUX11 = 1; //Enable TRIP3 Mux for Output
EDIS;
//-----------CHARGE-2-----------
// Config TB Moudle
EPwm11Regs.TBPRD = CHG_PWM_TBPRD; // Set ePWM12 count period value
EPwm11Regs.TBPHS.bit.TBPHS = CHG_PWM_PHASE1;
EPwm11Regs.TBCTR = 0x0000; // Clear counter
EPwm11Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count mode set UPDOWN
EPwm11Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Set UP count for counter
EPwm11Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading
EPwm11Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Load TB registers from shadow register
EPwm11Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio div 1
EPwm11Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Clock ratio div 1
EPwm11Regs.EPWMSYNCOUTEN.bit.ZEROEN = 0;
EPwm11Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_SYNCOUT_EPWM1; // SYNC source select ePWM1
// Config CC moudle
EPwm11Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load CC registers from shadow register
EPwm11Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // Load CC registers from shadow register
EPwm11Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // Load CC registers at TBCTR is Zero and Prd
EPwm11Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // Load CC registers at TBCTR is Zero and Prd
EPwm11Regs.CMPA.bit.CMPA = 1; // default set 1 for CMPA
EPwm11Regs.CMPB.bit.CMPB = 1; // default set 1 for CMPB
// Config AQ actions
EPwm11Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM11A on CMPA == TBCTR beside Up Count
EPwm11Regs.AQCTLA.bit.CAD = AQ_SET; // Set PWM11A on CMPA == TBCTR beside Dn Count
EPwm11Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM11B on CMPB == TBCTR beside Up Count
EPwm11Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM11B on CMPB == TBCTR beside Dn Count
EPwm11Regs.AQSFRC.bit.RLDCSF = 3; // Load AQ registers at TBCTR is Zero and Prd
EPwm11Regs.AQCSFRC.bit.CSFA = AQ_CLEAR; // Force Clear PWM11A
EPwm11Regs.AQCSFRC.bit.CSFB = AQ_CLEAR; // Force Clear PWM11B
EALLOW;
EPwm11Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm11Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm11Regs.TZFRC.bit.OST = 1;
EPwm11Regs.TZSEL.bit.DCAEVT2 = TZ_ENABLE;
EPwm11Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI;
EPwm11Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO;
EPwm11Regs.TZCLR.bit.CBCPULSE = 1;
EPwm11Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN3;
EPwm11Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm11Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;
EPwm11Regs.DCAHTRIPSEL.bit.TRIPINPUT3 = 1;
EDIS;
// Setup compare value for CMPC to generate SOCA
EPwm11Regs.CMPCTL2.bit.SHDWCMODE = CC_IMMEDIATE;//CC_SHADOW;
EPwm11Regs.CMPC = ADCDelay_DCDC;//72;
EPwm11Regs.CMPCTL2.bit.LOADCMODE = CC_CTR_ZERO;
EPwm11Regs.ETSEL.bit.SOCASELCMP = 1; // Enable CMPC/CMPD
EPwm11Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPC; // Select SOC on down-count
EPwm11Regs.ETSEL.bit.SOCAEN = 1; // enable SOC on A group
EPwm11Regs.ETPS.bit.SOCAPRD = 1; //1// Generate pulse on 1st event
//-----------CHARGE-3-----------
// Config TB Moudle
EPwm12Regs.TBPRD = CHG_PWM_TBPRD; // Set ePWM12 count period value
EPwm12Regs.TBPHS.bit.TBPHS = CHG_PWM_PHASE2;
EPwm12Regs.TBCTR = 0x0000; // Clear counter
EPwm12Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count mode set UPDOWN
EPwm12Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Set UP count for counter
EPwm12Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading
EPwm12Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Load TB registers from shadow register
EPwm12Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio div 1
EPwm12Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Clock ratio div 1
EPwm12Regs.EPWMSYNCOUTEN.bit.ZEROEN = 0;
EPwm12Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_SYNCOUT_EPWM1; // SYNC source select ePWM1
// Config CC moudle
EPwm12Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load CC registers from shadow register
EPwm12Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // Load CC registers from shadow register
EPwm12Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // Load CC registers at TBCTR is Zero and Prd
EPwm12Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // Load CC registers at TBCTR is Zero and Prd
EPwm12Regs.CMPA.bit.CMPA = 1; // default set 1 for CMPA
EPwm12Regs.CMPB.bit.CMPB = 1; // default set 1 for CMPB
// Config AQ actions
EPwm12Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM11A on CMPA == TBCTR beside Up Count
EPwm12Regs.AQCTLA.bit.CAD = AQ_SET; // Set PWM11A on CMPA == TBCTR beside Dn Count
EPwm12Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM11B on CMPB == TBCTR beside Up Count
EPwm12Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM11B on CMPB == TBCTR beside Dn Count
EPwm12Regs.AQSFRC.bit.RLDCSF = 3; // Load AQ registers at TBCTR is Zero and Prd
EPwm12Regs.AQCSFRC.bit.CSFA = AQ_CLEAR; // Force Clear PWM11A
EPwm12Regs.AQCSFRC.bit.CSFB = AQ_CLEAR; // Force Clear PWM11B
EALLOW;
EPwm12Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm12Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm12Regs.TZFRC.bit.OST = 1;
EPwm12Regs.TZSEL.bit.DCAEVT2 = TZ_ENABLE;
EPwm12Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI;
EPwm12Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO;
EPwm12Regs.TZCLR.bit.CBCPULSE = 1;
EPwm12Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN3;
EPwm12Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm12Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;
EPwm12Regs.DCAHTRIPSEL.bit.TRIPINPUT3 = 1;
EDIS;
// Setup compare value for CMPC to generate SOCA
EPwm12Regs.CMPCTL2.bit.SHDWCMODE = CC_IMMEDIATE;//CC_SHADOW;
EPwm12Regs.CMPC = ADCDelay_DCDC;//72;
EPwm12Regs.CMPCTL2.bit.LOADCMODE = CC_CTR_ZERO;
EPwm12Regs.ETSEL.bit.SOCASELCMP = 1; // Enable CMPC/CMPD
EPwm12Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPC; // Select SOC on down-count
EPwm12Regs.ETSEL.bit.SOCAEN = 1; // enable SOC on A group
EPwm12Regs.ETPS.bit.SOCAPRD = 1; //1// Generate pulse on 1st eventCould you please help reviewing the find where the issue is?
Regards,
Hang
