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TMS320F280049C: ADC Interrupt Missing during EFT Testing while using CLA Task

Bolt Hsieh
Prodigy 185 points

Part Number: TMS320F280049C

Hi experts,

I am using TMS320F280049C for a encoder application. I am facing an issue where the ADC interrupt (triggered to CLA) occasionally goes missing during EFT (Electrical Fast Transient) noise testing.

System Configuration:

  • Trigger Source: ePWM(period : 62.5us)

  • Processing: CLA Task 1 handles the ADC results.

  • ADC Configuration : ADC SOCs are configured in Round Robin mode from SOC0 to SOC7

  • ADC Settings:  INTPULSEPOS = 1 (Late Pulse), ADCINTSEL is triggered by SOC7.

  • Nesting: No interrupt nesting in C28x.

  • EFT Setting
    image.png

Symptoms:

  1. During EFT noise, the CPU interrupt (synchronized with the ADC trigger) is still firing correctly, which confirms the trigger source (ePWM) is active.

  2. However, the ADC stops generating interrupts to the CLA.

  3. The "Skip-Cycle" Phenomenon: During interference, the system exhibits a "Pass-Fail-Pass" pattern. The ADC successfully triggers the CLA on the 1st cycle, fails on the 2nd, and recovers on the 3rd.

  4. The CLA Task 1 is confirmed to have finished its previous execution before the next trigger.

Question 1: Potential ADC Logic/Sequencer Failure under EFT Is it possible for the internal ADC sequencer or digital logic to enter an undefined state or "latch-up" due to EFT (Electrical Fast Transient) interference? Specifically, can noise cause the ADC to stop generating EOC (End of Conversion) - ADCINT pulses even if the trigger source remains active?

Question 2: Diagnostic Register Snapshots for Root Cause Analysis In the event of a missing interrupt, which specific registers should be monitored to pinpoint the failure location? I am particularly interested in distinguishing between the following scenarios via register values:

  • Trigger Loss: (e.g., Checking ADCSOCFLG1 and ADCSOCOVF1)

  • Analog Power-down: (e.g., Accidental clearing of ADCPWDNZ in ADCCTL1)

  • Interrupt Blocking: (e.g., Analyzing the interaction between ADCINTFLG and ADCINTOVF)

Question 3: Mitigation and Fast Recovery Mechanisms (< 62.5µs) Are there recommended hardware configurations or software "watchdog" patterns to ensure ADC robustness against EFT? Furthermore, if a failure is detected, is there a documented high-speed re-initialization or "retry" procedure that can restore ADC operation within one control cycle (e.g., < 62.5µs for a 16kHz loop)?

Best regards,
Bolt

  • 0
    TI__Expert 5465 points

    Hi Bolt

    I do not think ADC sequencer goes in undefined state due to EFT interference. The interference may alter the ADC result at max.

    I see you are using an interface which tells you if the ADC triggers the CLA ISR. To make sure, Can you toggle a GPIO within the CLA ISR to make sure if the CLA ISR is really not triggered? If the problem persists, can you lower the PWM frequency to see if the issue still exists. Please let me know your findings. 

    Thank you 

    Amir Hussain