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TMS320F2809: Does Delaying XRS Prevent Power Sequencing Glitch?

Michael V
Intellectual 606 points

Part Number: TMS320F2809

Hello,

I have received a question from a customer regarding the power sequencing of the TMS320F2809NMFA.

Please refer to the following screenshot for information on a glitch that may occur if the 3.3V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.8V transistors. 

image.png

Based on this datasheet excerpt, my customer has the following question:

Q: If they were to use a reset IC with delay functionality to hold the XRS pin low until well after power-on, would this avoid the glitch outlined in Section 8.14.2? Or does the glitch occur regardless of the XRS pin's state? 

Best regards,

Michael

  • +1
    TI__Mastermind 38103 points

    Hi Michael,

    The safest answer is: holding XRS low alone may not reliably prevent the glitch. Proper power sequencing (VDD reaching 0.7V before VDDIO reaches 0.7V) is the recommended solution.

    Here's why there's ambiguity:

    The Case That XRS Might Help

    The datasheet's reset timing diagram (Figure 8-6) shows that while XRS is held low, GPIO pins are configured as inputs with their state determined by internal pull-up/pull-down resistors [1]. In theory, if the output buffers are not enabled (pins held as inputs), the glitch—which involves output buffers turning on—should not manifest externally.

    The Case That XRS Will Not Help

    The glitch described in Section 8.14.2 is a transistor-level hardware phenomenon: when the 3.3V transistors in the level-shifting output buffers power up before the 1.8V transistors, the output buffers can physically turn on [1][2]. This occurs at the analog/physical level during voltage ramp-up—potentially before the digital reset logic (controlled by XRS) is even functional. The datasheet's prescribed fix is exclusively power sequencing:

    "To avoid this behavior, power the VDD (core voltage) pins prior to or simultaneously with the VDDIO (input/output voltage) pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V." [1]

    Recommendation

    Do not rely on XRS delay alone. The customer should implement proper power sequencing:

    • Ensure VDD (1.8V) reaches 0.7V before VDDIO (3.3V) reaches 0.7V [1][2][3]
    • If deriving 1.8V from 3.3V (common with an LDO), consider using an FET switch to delay VDDIO connection until VDD is established [2]
    • The reset IC with delay is still good practice for meeting the separate XRS timing requirement (XRS must be held low for at least 1 ms after VDD reaches 1.5V) [1], but it should complement—not replace—proper sequencing
    Approach
    Prevents Glitch?
    Recommended?
    Power sequencing (VDD before VDDIO)
    Yes — documented solution
    Yes
    Holding XRS low during power-up
    Uncertain — not documented as mitigation
    Not as sole solution
    Both combined
    Best coverage
    Yes

    To help refine this recommendation, it would be helpful to know:

    • Whether the customer's power supply design allows VDD/VDDIO sequencing control
    • Whether they are deriving 1.8V from 3.3V (e.g., via LDO), which would make sequencing straightforward
    • Which specific I/O pins are critical and whether brief glitches would cause system-level issues

    1. TMS320F2809 Datasheet - Section 8.14.2 Power Sequencing
    2. TI Application Note SPRAAS1D - Hardware Design Guidelines for TMS320F28xx
    3. TI Application Note SLVA296A - Power Supply Requirements

    Best Regards,

    Zackary Fleenor