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TMS320F28P650DK: TMS320F28P650DK : CMPSS DACL to ADC loopback : offset behavior

Nicolas Jachimowicz
Prodigy 10 points

Part Number: TMS320F28P650DK

Hello, 

I am trying to implement the DAC to ADC loopback safety mechanism using CMPSS DACL such as mentionned in TRM. 

I have seen the topic raised in F28377D-SEP: ADC–DAC Loopback: Increasing Offset with Voltage on 

But in my case the offset are totally way beyond 100 counts difference, here some screenshot and read ADC is smaller than DAC generated from CMPSS

For 0xFFF in DACVALS of CMPSS1 : 

image.png

For 0x900 

image.png

 

For 0x200 : 

image.png

I expect at least ADC to saturate at 0xFFF 

Environnment context : 

DAC  is supplied via 3v3, and ADC is using internal reference 1v65, test was done on qualification board, as well as our product PCB with F28P65 embedded (results are the same)  

ADC are converted every 1ms using forced conversion by 

I am wondering what can be the root cause of this behavior (as everything is internal, no possibility to perform measurement) ? 

Thanks for the support ! 

  • 0
    TI__Expert 7750 points

    Hello,

    There are few checks I would recommend:

    For the internal CMPSS DAC loopback path, the ADC acquisition window needs to be much longer than a normal external ADC input. For similar C2000 ADCDACLOOPBACK usage, you need an acquisition requirement of about 4.3 µs.

    The CMPSS DAC is 12-bit, so the ideal output is approximately:

    Vdac = DACVAL / 4096.0 * VDDA

    The ADC result should then be compared against the corresponding ADC full-scale reference. If VDDA and ADC VREF are not exactly the same, some gain difference will appear.

    Keep in mind, this loopback is useful for connectivity/self-test and functional checking, but it should not be expected to match the DAC code exactly across the full range. I would suggest sweeping the DAC code across several points and plotting ADC result vs. DAC setting. If the error is mostly constant, it is likely offset. If it changes with code, it is gain/nonlinearity or settling related.

    Best Regards,

    Masoud

  • 0 in reply to Masoud Farhadi
    Prodigy 10 points

    Hi Masoud,

    Thanks for your feedback, indeed I have increased the acquisition time and the behavior is better, more stable read values.

    So there is no need to have an high accuracy to cover this safety mechanism, as depending on when the ADC is read the value can differ from 100 counts on my side but with same DAC value (of course with the calulated offset in the linear range) 

    CMPSS DACL output set -> 2 ms after -> ADC read (4.3µS aquisition time) 

    Thanks !