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TMS320F28388D: TMS320F28388D CLB ECAP setting

Mingi Park
Prodigy 10 points

Part Number: TMS320F28388D

Hello,

I'm tryting setting CLB TILES as the ECAP function.

I've refered and followed the example provided by TI, and been making my own PJT. 

(CLB and ECAP Lab )

 

  • Input signal matching: Real external pulse signal -> GPIO5 -> INPUTXBAR7 -> AUXSIG0 -> CLB XBAR MUX17 -> CLB1_BASE CLB_IN0/1/2
  • Configurate the TILE0 like the below

//---------------------------------------------------------------------------
// TILE0
//---------------------------------------------------------------------------
#define TILE0_PIPELINE_MODE 0
#define TILE0_CFG_OUTLUT_0 0x0
#define TILE0_CFG_OUTLUT_1 0x0
#define TILE0_CFG_OUTLUT_2 0x0
#define TILE0_CFG_OUTLUT_3 0x0
#define TILE0_CFG_OUTLUT_4 0x0
#define TILE0_CFG_OUTLUT_5 0x0
#define TILE0_CFG_OUTLUT_6 0x0
#define TILE0_CFG_OUTLUT_7 0x0

#define TILE0_CFG_LUT4_IN0   0x1498
#define TILE0_CFG_LUT4_IN1   0x6b40
#define TILE0_CFG_LUT4_IN2   0x0
#define TILE0_CFG_LUT4_IN3   0x0
#define TILE0_CFG_LUT4_FN10  ((0x88880000) | 0x5555)
#define TILE0_CFG_LUT4_FN2   0x8888

#define TILE0_CFG_FSM_EXT_IN0      0x19
#define TILE0_CFG_FSM_EXT_IN1      0x0
#define TILE0_CFG_FSM_EXTRA_IN0    0x0
#define TILE0_CFG_FSM_EXTRA_IN1    0x0
#define TILE0_CFG_FSM_NEXT_STATE_0 ((0xa5a50000) | 0x5a5a)
#define TILE0_CFG_FSM_NEXT_STATE_1 ((0x00000) | 0x0)
#define TILE0_CFG_FSM_NEXT_STATE_2 ((0x00000) | 0x0)
#define TILE0_CFG_FSM_LUT_FN10     ((0x00000) | 0xaaaa)
#define TILE0_CFG_FSM_LUT_FN2      0x0
#define TILE0_FSM_MISC_CONTROL     0x0

#define TILE0_CFG_COUNTER_RESET   0x359
#define TILE0_CFG_COUNTER_EVENT   0x0
#define TILE0_CFG_COUNTER_MODE_0  0xf8
#define TILE0_CFG_COUNTER_MODE_1  0x108

#define TILE0_CFG_TAP_SEL          0x0
#define TILE0_CFG_MISC_CONTROL    (0x0 | TILE0_FSM_MISC_CONTROL)

#define TILE0_COUNTER_0_MATCH1_VAL  0
#define TILE0_COUNTER_0_MATCH2_VAL  0
#define TILE0_COUNTER_0_LOAD_VAL    0
#define TILE0_COUNTER_1_MATCH1_VAL  0
#define TILE0_COUNTER_1_MATCH2_VAL  0
#define TILE0_COUNTER_1_LOAD_VAL    0
#define TILE0_COUNTER_2_MATCH1_VAL  0
#define TILE0_COUNTER_2_MATCH2_VAL  0
#define TILE0_COUNTER_2_LOAD_VAL    0


#define TILE0_SPI_EN 0

#define TILE0_HLC_EVENT_SEL 0x5f2f
#define TILE0_HLC_R0_INIT 0
#define TILE0_HLC_R1_INIT 0
#define TILE0_HLC_R2_INIT 0
#define TILE0_HLC_R3_INIT 0

void initTILE0(uint32_t base)
{
    uint16_t i;
    //
    //  Pipeline Mode
    //
    CLB_disablePipelineMode(base);
    //
    //  Output LUT
    //
    CLB_configOutputLUT(base, CLB_OUT0, TILE0_CFG_OUTLUT_0);

    CLB_configOutputLUT(base, CLB_OUT1, TILE0_CFG_OUTLUT_1);

    CLB_configOutputLUT(base, CLB_OUT2, TILE0_CFG_OUTLUT_2);

    CLB_configOutputLUT(base, CLB_OUT3, TILE0_CFG_OUTLUT_3);

    CLB_configOutputLUT(base, CLB_OUT4, TILE0_CFG_OUTLUT_4);

    CLB_configOutputLUT(base, CLB_OUT5, TILE0_CFG_OUTLUT_5);

    CLB_configOutputLUT(base, CLB_OUT6, TILE0_CFG_OUTLUT_6);

    CLB_configOutputLUT(base, CLB_OUT7, TILE0_CFG_OUTLUT_7);

    //
    //  AOC
    //
    CLB_configAOC(base, CLB_AOC0, TILE0_OUTPUT_COND_CTR_0);
    CLB_configAOC(base, CLB_AOC1, TILE0_OUTPUT_COND_CTR_1);
    CLB_configAOC(base, CLB_AOC2, TILE0_OUTPUT_COND_CTR_2);
    CLB_configAOC(base, CLB_AOC3, TILE0_OUTPUT_COND_CTR_3);
    CLB_configAOC(base, CLB_AOC4, TILE0_OUTPUT_COND_CTR_4);
    CLB_configAOC(base, CLB_AOC5, TILE0_OUTPUT_COND_CTR_5);
    CLB_configAOC(base, CLB_AOC6, TILE0_OUTPUT_COND_CTR_6);
    CLB_configAOC(base, CLB_AOC7, TILE0_OUTPUT_COND_CTR_7);

    //
    // LUT 0 - 2 are configured as macros in clb_config.h; these macros are used in
    // CLB_selectLUT4Inputs and CLB_configLUT4Function
    //
    //
    //  Equation for Look-Up Table Block 0 for TILE0: !i0
    //
    //  Equation for Look-Up Table Block 1 for TILE0: i0&i1
    //
    //  Equation for Look-Up Table Block 2 for TILE0: i0&i1

    //
    //  LUT Configuration
    //
    CLB_selectLUT4Inputs(base, TILE0_CFG_LUT4_IN0, TILE0_CFG_LUT4_IN1, TILE0_CFG_LUT4_IN2, TILE0_CFG_LUT4_IN3);
    CLB_configLUT4Function(base, TILE0_CFG_LUT4_FN10, TILE0_CFG_LUT4_FN2);

    //
    // FSM 0 - 2 are configured in <file>
    //
    //
    //  Output equation for Finite State Machine 0 for TILE0: s0
    //  State 0 output equation for Finite State Machine 0 for TILE0: s0^e0
    //  State 1 output equation for Finite State Machine 0 for TILE0: !(s0^e0)
    //

    //
    //  FSM
    //
    CLB_selectFSMInputs(base, TILE0_CFG_FSM_EXT_IN0, TILE0_CFG_FSM_EXT_IN1, TILE0_CFG_FSM_EXTRA_IN0, TILE0_CFG_FSM_EXTRA_IN1);
    CLB_configFSMNextState(base, TILE0_CFG_FSM_NEXT_STATE_0, TILE0_CFG_FSM_NEXT_STATE_1, TILE0_CFG_FSM_NEXT_STATE_2);
    CLB_configFSMLUTFunction(base, TILE0_CFG_FSM_LUT_FN10, TILE0_CFG_FSM_LUT_FN2);

    //
    // Counter 0 - 2 are configured in <file>
    //

    //
    //  Counters
    //
    CLB_selectCounterInputs(base, TILE0_CFG_COUNTER_RESET, TILE0_CFG_COUNTER_EVENT, TILE0_CFG_COUNTER_MODE_0, TILE0_CFG_COUNTER_MODE_1);
    CLB_configMiscCtrlModes(base, TILE0_CFG_MISC_CONTROL);

    CLB_configCounterLoadMatch(base, CLB_CTR0, TILE0_COUNTER_0_LOAD_VAL, TILE0_COUNTER_0_MATCH1_VAL, TILE0_COUNTER_0_MATCH2_VAL);
    CLB_configCounterLoadMatch(base, CLB_CTR1, TILE0_COUNTER_1_LOAD_VAL, TILE0_COUNTER_1_MATCH1_VAL, TILE0_COUNTER_1_MATCH2_VAL);
    CLB_configCounterLoadMatch(base, CLB_CTR2, TILE0_COUNTER_2_LOAD_VAL, TILE0_COUNTER_2_MATCH1_VAL, TILE0_COUNTER_2_MATCH2_VAL);
    CLB_configCounterTapSelects(base, TILE0_CFG_TAP_SEL);

    //
    // HLC is configured in <file>
    //

    //
    // HLC
    //
    CLB_configHLCEventSelect(base, TILE0_HLC_EVENT_SEL);
    CLB_setHLCRegisters(base, TILE0_HLC_R0_INIT, TILE0_HLC_R1_INIT, TILE0_HLC_R2_INIT, TILE0_HLC_R3_INIT);

    for(i = 0; i <= CLB_NUM_HLC_INSTR; i++)
    {
        CLB_programHLCInstruction(base, i, TILE0HLCInstr[i]);
    }
}

 

However, the counters do not work properly and need helps to improve it.

If anyone can review it, please give me feedback.

Best regards,

  • 0
    TI__Intellectual 1640 points

    Hi Mingi Park,
    Let me go through the configuration. I will get back to you shortly.
    Thanks
    Praneeth

  • 0 in reply to Venkata Praneeth Somina
    Prodigy 10 points

    Hi Praneeth,

    Thank you for your reply.

    My target system has the following requirements:

    • Measure pulse intervals from multiple independent input channels
    • Input signal frequency: approximately 1 MHz
    • Apply prescaling (1/25 ~ 1/30) to reduce event rate
    • Only frequency & period measurement is required (duty cycle is not needed)
    • All measurements should be performed autonomously inside the CLB
    • CPU should read the results asynchronously (e.g., via timer interrupt or ADC interrupt)
    • Avoid interrupt-driven capture for every event to minimize CPU load

    Initially, I reviewed the TI CLB + eCAP lab example.

    Thank you for your help and I look forward to hearing you.

  • 0 in reply to Mingi Park
    TI__Intellectual 1640 points

    Hi Mingi Park,
    I will keep in my mind the requirements you mentioned 
    Thanks
    Praneeth

  • 0 in reply to Venkata Praneeth Somina
    TI__Intellectual 1640 points

    Hi Mingi Park,
    I can see no even is selected to trigger counting. Match value in the counter are not set. Counter would not operate. These values need to be set for prescaling and frequency measurements.
    When you said counters are not working properly, can you please elaborate?
    Thanks
    Praneeth

  • 0 in reply to Venkata Praneeth Somina
    Prodigy 10 points

    Hi, Praneeth,

    The CLB counter does not increment during debugging, and its value remains constant, indicating that no counting activity is occurring.
    I just copied the code from the TI example (CLB and ECAP Lab), but as you said, it seems that there is no trigger and match event for counters.
    I still can’t figure out which part of the code needs to be modified...
    Could you please clarify which part of the configuration must be modified to properly generate a trigger so that the counter can start operating as intended?
    I don't think I've fully understanded CLB function, so if it is possible, could you please provide the full code or project for it?
  • 0 in reply to Mingi Park
    TI__Intellectual 1640 points

    Hi Mingi Park,
    I cannot provide a file for configuration but I can provide the screenshots of the configuration. I would recommend you to use syscfg for software development. I can provide a configuration which measures period and frequency as example. You can build from there. Does this work for you? It might take a couple of days to develop the logic. I will get back to you as soon as it done.

  • 0 in reply to Venkata Praneeth Somina
    Prodigy 10 points

    Hi Praneeth,

    Screenshots of the configuration in syscfg will be very helpful for me.

    Sincerely thank you for your help.

    Mingi

  • 0 in reply to Mingi Park
    TI__Intellectual 1640 points

    Hi Mingi Park,

    As you can see from above, I have enabled four inputs.

    I have selected an ePWM outputs as inputs to CLB Tile. Each input I have selected Rising edge, Falling edge for both channels, ePWM1A and ePWM1B.

    For Time period measurement, I have enabled the counter always. It will always count, because I have given Counter Enable 1. But the counter resets to zero when Input 3 pulse is received. Here Input 3 is the falling edge of EPWM1B.


    In HLC, when Input 3 pulse comes, the counter zero value will be loaded to register R0, which can be accessed by the software.
    From this accessed value, time period can be calculated.
    Similarly, you can find duty, phase shift between two pulses by appropriately configuring the CLB counters, Finite State Machines, High Level counters etc.
    I hope this helps you and enables you to do a lot of things with CLB.
    Thanks
    Praneeth