Other Parts Discussed in Thread: CONTROLSUITE
Hi,
in our design we use SPI/I2C/EPI (for SDRAM)/CAN/.../EMAC. According to TIs C2000 Pin Mux Utility (available in controlSUITE) everything should fit in the design; almost every pin is used.
We already have designed and produced a prototype and test right now the functionality of the different parts. Unfortunately we got an issue with the EMAC.
Usually we are using TIs example projects to test at least the basic functionality of the hardware. In this case we are using the enet_uip. To be sure if the programm is working, we checked it on the Concerto development board (enet_uip works like it is supposed).
First of all we changed the registers according to the information given in the pin mux utility and it did not work.
We checked the E2E Forum and found in "How to reset Ethernet PHY with Concerto MII" that we have to configure M_MIIPHYRST as GPIO. We have done this and checked if the signal shows the functionality. Ethernet connection is still not working.
So we changed the hardware pin assingment like it is given on the Concerto development board. We wanted to check if there is an issue with the tranceiver or the connector. In this case, the Ethernet was working.
We would like to ask if you could have a look at this. Please note that setting another pin assignment is not an option because we are already using every available pin on the Concerto.
Thanks in advance,
Andreas Beck
PS: Here is what we changed (compared to the original programm):
The following settings were made with the support of the C2000 Pin Mux Utility. We changed the registers PCTL and APSEL, like in the original program. Note: PHYRSTn is excluded here.
void EthernetPinsSetup(void){
//PORT D
// MII_TXD3
GPIODirModeSet(GPIO_PORTD_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
HWREG(GPIO_PORTD_BASE + GPIO_O_PCTL) &= 0xFFF0FFFF;
HWREG(GPIO_PORTD_BASE + GPIO_O_PCTL) |= 0x00040000;
//PORT E
// MII_RXD3, MII_MDIO, MII_TXER, MII_RXD0
GPIODirModeSet(GPIO_PORTE_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4, GPIO_DIR_MODE_HW);
GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4, GPIO_PIN_TYPE_STD);
HWREG(GPIO_PORTE_BASE + GPIO_O_APSEL)|= 0x000000E0;
HWREG(GPIO_PORTE_BASE + GPIO_O_PCTL) &= 0x0000FFFF;
HWREG(GPIO_PORTE_BASE + GPIO_O_PCTL) |= 0xCCC70000;
//PORT A
// MII_RXDV, MII_TXD0, MII_TXD1, MII_TXD2
GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2, GPIO_DIR_MODE_HW);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2, GPIO_PIN_TYPE_STD);
HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL) &= 0xFF0000FF;
HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL) |= 0x00333300;
//PORT B
// MII_RXD1, MII_CRS
GPIODirModeSet(GPIO_PORTB_BASE, GPIO_PIN_7|GPIO_PIN_6, GPIO_DIR_MODE_HW);
GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_7|GPIO_PIN_6, GPIO_PIN_TYPE_STD);
HWREG(GPIO_PORTB_BASE + GPIO_O_APSEL)|= 0x00000040;
HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL) &= 0x00FFFFFF;
HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL) |= 0x7C000000;
//PORT F
// MII_RXD2, MII_MDC, MII_RXER, MII_RXCK
GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_1|GPIO_PIN_0, GPIO_DIR_MODE_HW);
GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_1|GPIO_PIN_0, GPIO_PIN_TYPE_STD);
HWREG(GPIO_PORTF_BASE + GPIO_O_PCTL) &= 0xF0FF0F00;
HWREG(GPIO_PORTF_BASE + GPIO_O_PCTL) |= 0x03003044;
//PORT G
// MII_TXCK, MII_TXEN, MII_COL
GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_2, GPIO_DIR_MODE_HW);
GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_2, GPIO_PIN_TYPE_STD);
HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) &= 0xF00FF0FF;
HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) |= 0x03300300;
//PORT J
//Erata Sheet: Config PHYRSTn (PORTJ Pin 6) as GPIO
// MII_PHYRSTn , MII_PHYINTRn
GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
HWREG(GPIO_PORTJ_BASE + GPIO_O_APSEL)|= 0x00000040;
HWREG(GPIO_PORTJ_BASE + GPIO_O_PCTL) &= 0xF0FFFFFF;
HWREG(GPIO_PORTJ_BASE + GPIO_O_PCTL) |= 0x0C000000;
}
In the main - Loop we just set PortJ Pin 7 as Output (replace PHYRSTn) then set it to 0 before resetting the Ethernet Controller, then setting it again.
main - Loop:
//Init PortJ Pin 7 as Output (for PHYINTRn-Function)
GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_7);
GPIOPinTypeGPIOOutputOD(GPIO_PORTJ_BASE, GPIO_PIN_7);
GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_7, 0 /*GPIO_PIN_7*/);
// Enable and Reset the Ethernet Controller.
SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH);
GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_7, 0);
SysCtlPeripheralReset(SYSCTL_PERIPH_ETH);
GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_7, GPIO_PIN_7);
