TMS320F28075: Title: Issues with HRPWM implementation in Up-Down Count Mode on TMS320F28075

SUNGHO CHA

Hello,

I am currently developing a product using the TMS320F28075 and have a question regarding HRPWM configuration in Up-Down Count mode.

I am generating a symmetrical PWM signal based on TBPRD using only CMPA in Up-Down Count mode. My goal is to apply HRPWM (High-Resolution PWM) to both sides of the TBPRD reference to achieve finer control over the minimum duty cycle.

I have attached my PWM configuration code for your reference.

    EPwm1Regs.TBPRD = (PWMCLK / EPWM1_TMN_SM_0_Freq)>>1;       // Set timer period 705 TBCLKs
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                  // Clear counter

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Enable phase loading for sync signal receive
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;    

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero

    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;            // Set PWM1A on event A, up count
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;          // Clear PWM1A on event A, down count
    EPwm1Regs.CMPA.bit.CMPA = ((PWMCLK / EPWM1_TMN_SM_0_Freq)>>1)*0.95;                 //initiate

    EALLOW;
    EPwm1Regs.HRCNFG.all = 0x0;                        // Clear all bits first
    EPwm1Regs.HRCNFG.bit.EDGMODE  = HR_REP;            // MEP control on Rising edge
    EPwm1Regs.HRCNFG.bit.CTLMODE  = HR_CMP;            
    EPwm1Regs.HRCNFG.bit.HRLOAD   = HR_CTR_ZERO_PRD;   
    EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;                 
    EPwm1Regs.HRPCTL.bit.HRPE     = 0;                
    EDIS;

I have attempted to apply HRPWM, but I am encountering issues where it does not seem to apply symmetrically across TBPRD. As shown in the attached waveform, the HRPWM effect is only visible on the right side.

Red (ePWM7A): This is the reference signal with the same CMPA value (without HRPWM).
Yellow (ePWM1A): This is the signal with HRPWM applied.

EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP;

2. EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP

Is it possible to configure the HRPWM to also be applied to the left side (as seen in waveform #1)? If so, could you please advise on the necessary settings or adjustments?

Thank you for your assistance.

4 months ago

0 SUNGHO CHA 4 months ago

Prodigy 40 points

Sorry. The content in the last sentence is incorrect.

As you can see, the HRPWM effect is only being applied to the right side of the waveform. I would like to know if there is a way to configure the HRPWM so that it is also applied to the left side relative to the TBPRD center. Could you please advise on the necessary settings or registers to achieve symmetric HRPWM in Up-Down Count mode?

0 Allison Nguyen 4 months ago in reply to SUNGHO CHA

TI__Mastermind 27540 points

Hello Sungho Cha,

Please allow another 1-2 days for me to review all of your information and formulate my response. Appreciate your patience.

Best Regards,

Allison

0 Allison Nguyen 4 months ago in reply to SUNGHO CHA

TI__Mastermind 27540 points

Hi Sungho Cha,

"HR_REP" applies MEP only to the up-count CMPA match (rising edge); "HR_FEP" only to the down-count match (falling edge). Neither controls both edges.

You need to change EDGMODE to "HR_BEP" (Both Edge Position = 3):

EALLOW;

EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // Both edges — MEP fires at Counter A on up-count and Counter A on down-count
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;
EPwm1Regs.HRPCTL.bit.HRPE = 0;

EDIS;

In Up-Down Count mode with HR_BEP + CTLMODE = HR_CMP, the CMPAHR fractional extension raises the effective threshold for both the up-count and down-count CMPA events. The rising edge delays and the falling edge advances by the same MEP fraction — symmetric around TBPRD.

Ensure that SFO() is running in a background loop to keep HRMSTEP calibrated. Without a valid HRMSTEP, AUTOCONV = 1 will produce incorrect MEP scaling.

As reference for this info: TMS320F2807x TRM SPRUHM9H section §14.14.1.3, p.1846–1847.

Best Regards,

Allison

0 SUNGHO CHA 4 months ago in reply to Allison Nguyen

Prodigy 40 points

Hello. Allison

What I need is for the operation to be advanced, not delayed, at the rising edge.

Is there really no way to implement an advancement at the rising edge when using HRPWM?

Best Regards,

0 Allison Nguyen 4 months ago in reply to SUNGHO CHA

TI__Mastermind 27540 points

Hi Sungho Cha,

Keep in mind HRPWM cannot directly advance an edge — the MEP only adds delay from the integer CMPA boundary. However, edge advancement is fully achievable by decrementing CMPA by 1, then using CMPAHR to delay back to the desired position. With this, the effective edge position = (CMPA - 1) + (CMPAHR/255 × T_TBCLK)

For example, to advance the rising edge by 0.3 TBCLK from its current position:

Set CMPA = original_CMPA - 1
Set CMPAHR = round(0.7 × MEP_ScaleFactor)

If you are using autoconversion (AUTOCONV = 1), this is handled automatically — write a smaller fractional duty cycle value and the hardware will split it into the correct CMPA (integer) and CMPAHR (fractional) combination. No special register configuration is needed beyond what you already have.

Best Regards,

Allison

0 SUNGHO CHA 4 months ago in reply to Allison Nguyen

Prodigy 40 points

Hello, Allison.

Thank you for the explanation. I understand it clearly.

Best regards,

Cha

0 Allison Nguyen 4 months ago in reply to SUNGHO CHA

TI__Mastermind 27540 points

Glad to hear!

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TMS320F28075: Title: Issues with HRPWM implementation in Up-Down Count Mode on TMS320F28075