Part Number: C2000WARE
Other Parts Discussed in Thread: TMS320F28379D
CLB Deadband Implementation Using GPIO Inputs on TMS320F28379D
Hi,
I am working on the CLB (Configurable Logic Block) of the TI C2000 TMS320F28379D using Example 1 – Combinatorial Logic. However, instead of using ePWM inputs, I have configured GPIOs as follows:
GPIO Configuration:
GPIO50 → Mode 0 control → INPUTXBAR1
GPIO52 → Mode 1 control → INPUTXBAR2
GPIO0 → CLB Input 1 → INPUTXBAR3
GPIO1 → CLB Input 2 → INPUTXBAR4
CLB XBAR Mapping:
AUXSIG0 → INPUTXBAR1
AUXSIG1 → INPUTXBAR2
AUXSIG2 → INPUTXBAR3
AUXSIG3 → INPUTXBAR4
Output Configuration:
GPIO2 → CLB Output via: OUTPUT1XBAR → CLB1_OUT4
GPIO3 → CLB Output via:OUTPUT2XBAR → CLB1_OUT5
CLB Input Mux Setup
IN0 mux → AUXSIG0
IN1 mux → AUXSIG1
IN2 mux → AUXSIG2
IN3 mux → AUXSIG3
CLB Output Routing
OUT4 → Routed to XBAR
OUT5 → Routed to XBAR
I am using the same clb_config.c and clb_config.h files with minor modifications to the output LUT configuration, since I am utilizing outputs 4 and 5.
Current Behavior
The setup is working as expected:
* I provide a square wave to GPIO0
* Its inverted signal is applied to GPIO1
* The CLB processes the logic correctly with Active High Logic and I'm getting output at GPIO2 and GPIO3.
Requirement:
I would like to implement a deadband (non-overlapping delay) between the complementary (logical opposites of each other) outputs.
Can deadband be implemented using the CLB counter module?
Or is there any other recommended approach within CLB or without CLB counter block to achieve this? could you please help me with that if possible?
Please refer attached diagram to see what I'm expecting:
This is taken from CLB Tool User's Guide.
