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TMS320F280025C: F280025 LIN SCI mode baud rate inconsistency clarification

Filipe Carneiro
Prodigy 40 points

Part Number: TMS320F280025C
Other Parts Discussed in Thread: TMS320F280025

Hi,

I am working with the LIN module in SCI compatibility mode on the TMS320F280025, and I am trying to understand how the baud rate generator works. While reviewing the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual, revised March 2024, I found some inconsistencies that I would like clarification on.

On page 96, the imagesshows that the LIN module is fed by PERx.SYSCLK, which is equal to SYSCLK.
On page 2456, it also states that "LIN VCLK is equal to the SYSCLK frequency".

On page 2460, it states "In the asynchronous timing mode, each bit in a frame has a duration of 16 SCI baud clock periods".

On page 2454, it states that "At 100MHz peripheral clock, 3.125Mbits/s is the maximum baud rate achievable".

On page 2461, the following formulas are presented:

"SCICLK Frequency = VCLK Frequency / (P+1+M/16)  (1)

Asynchronous baud value = SCICLK Frequency/16       (2)


For P = 0,
Asynchronous baud value = VCLK Frequency/32          (3)"

Inconsistencies:
a) Where did the "32" in equation (3) come from? Combining (1) and (2) for P = M = 0 results in baud = VCLK / 16
b) If VCLK = SYSCLK and 1 bit = 16 SCICLK pulses, the maximum achievable baud rate for 100 MHz would be 6.250Mbits/s

Questions:

  1. What exactly is VCLK for the LIN module on F28002x? Is it truly SYSCLK, or is there an implicit division before the baud generator?

  2. Is the duration of the bit 16 or 32 SCICLK cycles?

  3. Is the correct effective formula for baud actually: baud = VCLK / [32 × (P + 1 + M/16)] ?

  4. In conclusion, if SYSCLK = 20 MHz, is the maximum achievable baud rate 625 kbit/s?

Thanks in advance for the clarification.

Best regards,
Filipe

  • 0
    TI__Mastermind 27540 points

    Hi Filipe,

    1. VCLK for the LIN module is SYSCLK directly — no implicit division. On F28002x, the LIN modules (LINA, LINB) receive PERx.SYSCLK with no prescaler before the baud generator. The TRM statement "LIN VCLK is equal to the SYSCLK frequency" is accurate. 
    2. Each bit is always 16 SCICLK periods. However, when P = 0, the hardware enforces a minimum prescale of 2, meaning SCICLK = VCLK/2 at that setting. The bit period at P = 0 is therefore 16 × (2 × T_VCLK) = 32 × T_VCLK. This is explicitly confirmed in §24.2.1.3.1: "For P = 0, T_bit = 32 T_VCLK."
    3. The correct formulas are: baud = VCLK / 32 for P = 0, and baud = VCLK / [16 × (P + 1 + M/16)] for P ≥ 1. Equations (1) and (2) in the TRM are valid for P ≥ 1 only. For P = 0, the hardware minimum prescale of 2 prevents a divide-by-1, and equation (3) — baud = VCLK/32 — takes precedence.
    4. Yes, at SYSCLK = 20 MHz the maximum achievable baud rate is 625 kbps. baud_max = VCLK / 32 = 20 MHz / 32 = 625 kbps. This is consistent with the TRM's stated maximum of 3.125 Mbps at 100 MHz (100 MHz / 32 = 3.125 Mbps).

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Prodigy 40 points

    Hi Allison,

    Now it's clear. Thank you for your answer!


    As a suggestion for a future revision of the TRM, I think it would help to explicitly state that equation (3) applies specifically for P = 0, while equation (2) applies for P ≥ 1. As it is currently written, it gives the impression that equation (3) is simply derived by substituting P = 0 into equation (2), which can be misleading.

    Thank you for your support.

    Best regards,
    Filipe

  • 0 in reply to Filipe Carneiro
    TI__Mastermind 27540 points

    Thanks for the feedback, Filipe! Filing a note to make the clarification Slight smile