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TMS320F28P659DK-Q1: FSI Speed issue

Kita Li
Expert 3445 points

Part Number: TMS320F28P659DK-Q1

Hi,

 

I am asking an urgent request from customer.

My customer is using FSI, the FSI of the F28P65 chip has 3 signal lines per port: a clock line CLK, and data lines D0 and D1. The data line D1 can be used to double the data transfer rate. Is it necessary to add this D1 signal if they want a higher speed communication? And what is the data rate with/without D1?

 

Best Regards

Kita 

  • 0
    TI__Mastermind 33653 points

    Hello Kita,

    Thank you for your inquiry regarding FSI data rates on the TMS320F28P659DK-Q1.

    FSI Data Rates:

    With D1 enabled (3-wire configuration: CLK, D0, D1):

    • Maximum data rate: 200 Mbps at 50 MHz CLK frequency

    Without D1 (2-wire configuration: CLK, D0):

    • Maximum data rate: 100 Mbps at 50 MHz CLK frequency

    Is D1 necessary for higher speed communication?

    The D1 signal line is optional. Adding D1 effectively doubles the data transfer rate from 100 Mbps to 200 Mbps. Whether your customer needs to add D1 depends on their bandwidth requirements:

    • If 100 Mbps is sufficient for their application, they can use the 2-wire configuration (CLK + D0 only)
    • If they require higher throughput up to 200 Mbps, they should implement the 3-wire configuration (CLK + D0 + D1)

    Both configurations utilize DDR (Dual Data Rate) transmission on rising and falling clock edges. The D1 line simply provides an additional data path to double the effective bandwidth.

    Please let me know if your customer needs additional clarification or has further questions about FSI configuration.

    Best Regards,
    Zackary Fleenor

  • 0 in reply to Fleenor
    TI__Expert 3445 points

    Hi Fleenor,

    I want to know where 100 Mbps/200 Mbps shown in datasheet/TRM/documents?

    Best Regards

  • 0 in reply to Kita Li
    TI__Mastermind 33653 points

    Hi Kita,

    This is shown on the very first page of the datasheet:

    It can be found again here in the description section:

    The throughput values are assumed based on the maximum clock frequency (50MHz) and 2x Dual Data Rate data lines.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    TI__Expert 3445 points

    Hi Fleenor,

    I suggest to add 100 Mbps at 50 MHz CLK frequency without D1 in datasheet. Customer is confused on this.

    Best Regards

  • 0 in reply to Kita Li
    TI__Mastermind 33653 points

    Hi Kita,

    This is assumed based on the terminology "up to" 200Mbps, which means the IP can support Mbps less than 200Mbps, including 100Mbps. 100Mbps could also be achieved by using a 25MHz clock with both D0 and D1. We use this terminology due to the flexibility and variations provided by the SoC/IP.

    Best Regards,

    Zackary Fleenor