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TMS320F28P650DK: Current consumption spec vs internal VREG

Andy Alexander
Prodigy 170 points

Part Number: TMS320F28P650DK

I'm having trouble making sense of the "VREG Enabled" vs "VREG Disable - External Supply" specs in the datasheet (SPRSP69D – JULY 2023 – REVISED AUGUST 2025).

If I understand the internal power architecture correctly, VDDIO (3.3V) feeds the internal VREG which, when enabled, can supply the VDD (1.2V).  Also, I understand that the internal VREG is a linear regulator.

It seems that when VREG is enabled that IDDIO (measured externally) should be the sum of the internal IDDIO (for the IO and other uses) + IDD (from VREG, to the core).

When VREG is disabled and an external VDD is used, IDDIO + IDD should be roughly the same at the total IDDIO when VREG is enabled.

I do understand that the total power into the chip drops when VREG is disabled and an external regulator used, which makes sense.

I don't understand why it seems that the 1.2V supply's current seems to increase when using an external VDD regulator -- it's counterintuitive.

Could you explain why this spec is written this way?  Examples from the two areas of the datasheet are below.

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  • 0
    TI__Mastermind 26620 points

    Hi Andy,

    The expert for this topic is currently out of office, please expect a delayed response.

    Best Regards,

    Delaney

  • +1 in reply to Delaney Woodward
    TI__Guru* 86210 points

    Andy,

    Thanks for reaching out, this is one of those parameters that is not intuitive without some background from TI.

    You are correct in terms of how the regulator is implemented, LDO type/derived from the VDDIO supply when in use.

    The disconnect in the total current comes from a difference in the VDD max that the device will see when the VREG is on/off.

    When the VREG is disabled; then the current we list as IDDmax; occurs at the VDD max specification in the DS at 1.32V.

    When the VREG is enabled, the internal LDO is trimmed such that it is centered at 1.2V; but over the full VDDIO range it does not swing across the full tolerance, even though it would be allowed. 

    As such, the current consumed more closely mimics that of a VDD = 1.2V always; and as such created a lower overall IDDIO max in this case vs the VREG disabled case IDDIO + IDD.

    Best,

    Matthew