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TMS320F280049C: Behavior of ADC result register

xu chunlei
Prodigy 140 points

Part Number: TMS320F280049C

Hi, 

     I use TMS320F280049C to configurate ADC-A: SOC0, SOC1,SOC2,SOC3 to sample different analog signals. And set up SOC1 for ADC interrupt trigger source.

   And in related ADC ISR(triggered by SOC1) to collect all data(include SOC2 and SOC3), my question is: is there any issue about this method?  I know when at the time read SOC2 and SOC3 ADC result register, the SOC2 and SOC3 maybe have not complete ADC conversion, so what's the value in SOC2 and SOC3 result register? the value is zero? or it will keep the previous value(if previous have value not zero)?

     Another question is how much time will it take for write the ADC value to ADC result register when finish ADC conversion? Is there any possible when CPU read the ADC result register conflict with writing to result register?

  • 0
    TI__Mastermind 44690 points

    Hi xu,

    If trigger source for SOC0-SOC3 is the same, it would be best to trigger the ISR by the last SOC (SOC3) so that when results are read in the ISR, you are assured that SOC0 to SOC3 results are up to date.  If trigger source is the same, SOC0 will convert first and at the end of tLAT (refer to timing diagram in datasheet), the conversion results are available at the ADCRESULTx register.  After SOC0 converts, SOC1 will follow, then SOC2 and SOC3 and it follows that ADCRESULT0 will be updated first, then ADCRESULT1 to ADCRESULT3.  If SOC has not finished conversion yet at any time prior to tLAT, the ADCRESULTx register will contain the previous conversion result.

    Writing to the ADC result register only happens after  tLAT when conversion finishes ( tEOC refer to timing diagrams and tables in the datasheet).  To ensure that latest results are read after, on do the ADC reads after tLAT.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Prodigy 140 points

    Hi Joseph,

    In our current design we didn't set the ADC ISR triggered by the last SOC(SOC3) due to some requirement.  we just set up SOC1 for ADC interrupt trigger source. But we want to know if I get all  ADCRESULTx register in this ISR,  is there any conflict  when CPU is reading SOC2 and SOC3 result register data  while Haradware is wring data into  result register at the same time ,so I will get a wrong data not a previous conversion result.

  • +1 in reply to xu chunlei
    TI__Mastermind 44690 points

    Hi xu,

    There is no possibility of getting the wrong data due to the pipeline being busy during ADC result write operation as read are not allowed during that time.  Read will be in queue and will proceed once the write operation has finished.

    Regards,

    Joseph