AM13E23019: How MCU handle the interrupt with the same priority

Joe Ji

Part Number: AM13E23019
Other Parts Discussed in Thread: SYSCONFIG

Hi Expert

There are 2 questions:

#1 is interrupt round-robin rule

Want to ask the Interrupt use case: there are 3 interrupts: PWM INT1/ SPI INT2/ Timer INT3.

INT1 and INT2 set to the same priority1, and INT3 set to the lower priority2.

There is a case:

1.CPU is running INT3,

2.INT1 and INT2 come at the same time

3.INT1 comes again following "2"

According to TRM CPU->Interrupt section, when "2" happens, CPU will store INT3 in stack and serve INT1 and INT2 this process is controlled by NVIC.

The question is when "2" ends and CPU runs INT3 again and "3" happens, will INT1 can interrupt INT3 again, or it need to wait for INT3 finish?

#2 is what is Default Interrupt Priority in sysconfig? there is no details in TRM, is it something in CMSIS?

Thanks

Joe

+1 Shaunak Deshpande 3 months ago

Hi Joe,

Q1 — INT1 and INT2 occur simultaneously with the same priority. Which is serviced first?

Both INT1 and INT2 arrive simultaneously and are pending in the NVIC.
Since Priority(INT1) == Priority(INT2), priority alone cannot break the tie.
The NVIC uses IRQ number (vector number) as the tiebreaker — the interrupt with the numerically lower IRQ number is selected first. This is called natural order arbitration.
The selected interrupt preempts INT3 (which has lower priority), stacks INT3's context, and runs its ISR.
After the first ISR completes, the NVIC uses tail-chaining — it does NOT unstacks and re-stacks. It directly fetches the next pending vector and executes the second ISR
Key ARM reference: ARMv8-M Architecture Reference Manual, Section B3.4 — "If two pending exceptions have the same priority, the one with the lower exception number takes priority."

INT-3 will be starved, Only if INT1 (or INT2) keeps firing repeatedly and indefinitely faster than it can be serviced, such that every time the NVIC is about to resume INT3, a new higher-priority interrupt is already pending. In that case, INT3 would never get CPU time, that is true starvation. Flow would be something like:[INT3 ISR running]
→ INT1 + INT2 arrive simultaneously
→ INT3 preempted (stacked/suspended)
→ INT1 runs first (lower IRQ#)
→ INT1 completes → tail-chain to INT2
→ INT2 completes → INT1 arrives again (new pending)
→ INT1 runs again (higher priority than INT3)
→ INT1 completes → no more high-priority interrupts
→ INT3 resumes and completes

Joe Ji said:
#2 is what is Default Interrupt Priority in sysconfig? there is no details in TRM, is it something in CMSIS?

By default the example.syscfg has some interrupt priorities setup for peripherals by default,

When adding a new interrupt, you can also set the priority manually:

Regards,
Shaunak