F29H850TU: Real-time off-chip pin trace

Part Number: F29H850TU
Other Parts Discussed in Thread: TMDSEMU110-U, TMDSEMU200-U

Hi,I have three questions regarding debug and trace on the F29H850TU:1. The TRM (SPRUJ79) has Chapter 16 (ERAD) for on-chip PC trace via ETB and Chapter 17 (DLT) for data logging — but no chapter for TPIU or off-chip pin trace. Does this mean off-chip pin trace is not supported and trace is limited to on-chip ETB/ERAD/DLT only?2. The supported-device lists on the XDS110, XDS200, and XDS560v2 product pages do not include F29H850TU. Which XDS debug probe is officially validated for this device? We currently have an XDS200 and would like to know if it can connect before purchasing a new probe.3. Is simultaneous multicore debug of all three C29x cores supported in CCS with any XDS probe, or does the SSU zone authentication require a specific tool?Thank you.

  • Hi,

    but no chapter for TPIU or off-chip pin trace. Does this mean off-chip pin trace is not supported and trace is limited to on-chip ETB/ERAD/DLT only

    This is correct. 

    The supported-device lists on the XDS110, XDS200, and XDS560v2 product pages do not include F29H850TU

    XDS110 and XDS200 supports F29x devices. On which portal you are referring the list of supported device ?

    Is simultaneous multicore debug of all three C29x cores supported in CCS with any XDS probe, or does the SSU zone authentication require a specific tool?

    Can you elaborate a bit more on simultaneous debug of all three cores ? This is more of IDE feature. Right ? 

    Vivek Singh

  • Hi Vivek,

     

    Thank you for the clarification.

     

    Regarding the supported-device list: I was referring to the supported products tab on the following TI product pages:
    • www.ti.com/.../TMDSEMU110-U
    • www.ti.com/.../TMDSEMU200-U

     

    F29H850TU does not appear in the supported-device list on either page. It is good to know that both XDS110 and XDS200 support F29x devices despite not being listed there — it would be helpful if those pages could be updated.

     

    Regarding multicore debug: I understand that this is primarily an IDE (CCS) feature rather than probe-specific.

    To confirm my understanding:

    With an XDS200 connected to the F29H850TU, is it possible within a single CCS debug session to connect to all three C29x cores simultaneously and control them together (e.g. using synchronized breakpoints or global run/halt)?

     

    Additionally, is there any limitation imposed by the SSU (security configuration) that could affect simultaneous access to all cores during debugging?

     

    Thank you, 
    Farzaneh
  • Thanks.

    Regarding the supported-device list: I was referring to the supported products tab on the following TI product pages:

    I have reported this to our debug team.

    With an XDS200 connected to the F29H850TU, is it possible within a single CCS debug session to connect to all three C29x cores simultaneously and control them together (e.g. using synchronized breakpoints or global run/halt)?

    Yes, that should work. 

    Additionally, is there any limitation imposed by the SSU (security configuration) that could affect simultaneous access to all cores during debugging?

    SSU is like MPU so it should not cause any issue with general debug unless user has configured SSU to block any JTAG access.

    Vivek Singh