Part Number: TMS320F28P550SJ
Other Parts Discussed in Thread: SYSCONFIG
Hi Experts,
My customer is using SPI (master) + DMA. Where TXFFST < TXFFIL (0x1) would triggers SPITXDMA, and DMA moves the data from buffer to TXFIFO. The trnasfer size is set as 128.
The design is, when FIFO is empty (<1), DMA is triggered moves data in TX FIFO, then TXFFST=1. SPI shfit the data out, TXFFST=0, DMA triggered again. This repeats until DMA moves 128 data as the channel is stopped.
The problem is, the first SPITXDMA is not triggered. After I initlize SPI and DMA, my states are like below:
- nothing in the SPI TX FIFO, and TXFFST< TXFFIL.
- The DMA is started, RUNSTS=1, but PERINTFLG is not set,
- Next, I write 1 to PERINTFRC. Once I write 1 to it, the DMA is triggered, and it's repeatively triggered by SPITXDMA, until it finish the whoe transfer.
This indicates that the first trigger of SPITXDMA is missed. What's the problem here?
We are aware that the ex5_loopback_dma can achieve this design. But we need to find the root cuase so that customer can fix their own code.
I have the customer code snipet and reproduced it with the below project.
spi_ex5_loopback_dma_hunkey.zip
This thread mentioned the SPITXDMA is edge sensitive but I can not find more information.
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