LAUNCHXL-F28379D: EPWM Synchronization with EXTSYNC1

Hi Imrose
Are you using HRPWM? If yes the jitter is expected behavior. To eliminate this, a software synchronization pulse should be issued only once during high-resolution period initialization. TBCTL[SYNCOSEL] must not be set to 1 (CTR=0) or 2 (CTR=CMPB) when HRPWM period mode is enabled — otherwise jitter occurs every cycle.
If standard PWM is being used, Jitter can creep in because of 5MHZ frequency. As this is an async signal, the phase load can only happen at next clock cycle. And the tolerance in 5MHz signal can also aid this.
I would recommend to use HRPWM to minimize the jitter. 
These E2Es already discussed how to overcome this problem (+) TMS320F28379D: Problem with phase shift - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums
(+) TMS320F28379D: Jitter on HRPWM output - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums
Thanks
Praneeth

Hi Praneeth,

The jitter in my case persists even after disabling the HRPWM. I have configured the HR module to use the high-resolution phase shift. The phase shift register values do not change dynamically; they are set once during initialization. I have attached a figure of the jitter I see. The yellow waveform is the external pulse, and the blue one is the PWM signal. Oscilloscope trigger is set to the blue waveform.

I think your second comment applies to my case. Because of the async signal, I am seeing this +-1-tick jitter. To verify this, I have set ePWM1 as the master and provided its output to ePWM4 as EXTSYNC2. As expected, jitter completely disappears from the PWM signal in this case.

However, since my goal is to synchronize with the external signal, I will have to deal with this jitter. You have mentioned that I can use HRPWM to minimize this jitter. Could you please elaborate on this? Will it be possible to reduce this jitter to +-1 ns, for example?

Thanks,

Imrose

Hi Imrose,

If your sync in pulse is an external async signal, there will be a minimum jitter of 1 TBCLK. Will check and get back on how this can be reduced.

Regards,
Harisyam

Hi Harisyam,

Looking forward to your comments.

Thanks,

Imrose

Hi Imrose, 

I am out of office. Apologies for the delay. Please give me a day or two. I will get back to you. 

Thanks

Praneeth

Hi Imrose
I have tested with HRPWM, I could not bring the jitter to values less than 1 TBCLK. This is because of 5MHz external Sync signal. So a 1 TBCLK signal will be there at this frequency.
Thanks
Praneeth