• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 82 subscribers
  • Views 131 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P650DK: CLB Synchronization Requirement

LIU LIU
Intellectual 410 points

Part Number: TMS320F28P650DK

Hi TI support team,

Based on Figure 12-3 in TMS320F28P65x TRM, CLB Clock can be configured to SYNMODE or ASYNMODE with the SYSCLK. When I configure CLB to ASYNCMODE:

  1. Is Column Synchronization Requirement of Table 12-2. Global Signals and Mux Selection still valid?
  2. IF the input signal comes from other modules, I need configure CLB_INPUT_FILTER.SYNC =1 , instead of referring to the Table 12-2?
  3. If I misunderstand, please explain why comlumn Synchronization Requirement of Table 12-2 is still valid in ASYNCMODE
  • 0
    TI__Expert 3160 points

    Hi Liu
    Thanks for reaching out. I will get back to you in a day or two.

  • +1 in reply to Venkata Praneeth Somina
    TI__Expert 3160 points

    Hi Liu,
    1. Even when CLB is in ASYNC mode of clocking, synchronization requirements of the table are still valid. 
    2. No, as per the requirements in table, SYNC bit should be enabled/disabled
    3. Confusion is because of the naming, SYNC and ASYNC mode. Even in ASYNC mode, Tile clock's edges are phase aligned with SYSCLK, it is just that the frequencies are different. Because of this the Synchronization Requirement given in the table is still valid in ASYNCMODE.
    Thanks
    Praneeth

  • 0 in reply to Venkata Praneeth Somina
    Intellectual 410 points

    Hi Venkata,

    1. I think PLLSYSCLK and AUXPLL are asynchronous clk based on Figure 3-5. Because the clock source of PLLSYSCLK source is determined by the configuration of OSCCLKSRCSEL and the clock source of AUXPLL source is determined by the configuration of AUXOSCCLKSRCSEL. 

    2. Why you think Tile clock's edges are phase aligned with SYSCLK? For Example, SYSCLK and Tile clock are asynchronous clk when configuration of OSCCLKSRCSEL and AUXOSCCLKSRCSEL is both 10. 

  • +1 in reply to LIU LIU
    TI__Expert 3160 points

    Hi Liu,
    Yes, you are right when AUXPLL and SYSCLK are not in phase. 
    Synchronization and Pipeline mechanisms give inputs to tile. Tile clock depends on the mode of operation, Sync/Async. Synchronizer and Pipeline mechanism have different clock domain from Tile. 
    Thanks 
    Praneeth