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TMS320F28377D: Clarification on Power Sequencing Requirements and Tolerances

Michael V
Intellectual 546 points

Part Number: TMS320F28377D
Other Parts Discussed in Thread: LAUNCHXL-F28379D, LM4132

Hello,

I'm looking for clarification regarding the power sequencing requirements for the TMS320F28377D.

I have already reviewed the datasheet and understand the following requirements:

  • The 3.3V supply rails (VDDIO, VDDA, VDD3VFL, VDDOSC) should remain within 0.3 V of each other.
  • VREFHI should not exceed VDDA + 0.3 V.
  • 3.3V supply rails should be powered up together.

However, I would like clarification regarding these requirements specifically during the power-up and power-down transitions.

 

Currently, I have a customer who is testing a custom board that uses a single 5-V source that powers:

A 3.3-V LDO, which supplies:

  • VDDA
  • VDDIO
  • VDD3VFL

A precision reference IC, which supplies:

  • VREFHI
  • VDDOSC
Because the LDO and reference IC have different startup and shutdown characteristics, there are brief periods during power-up and power-down where the voltage difference between these rails exceeds 0.3 V.
 
On both power-up and power-down, I am observing the LDO occasionally leading the reference IC by up to 0.8V, despite both devices beginning to transition at the same time.
 
Questions: 

1.What exactly is meant by the requirement that the 3.3V rails be powered simultaneously?

I could not find any specification defining:

  • Maximum allowed startup delay between rails
  • Maximum allowed power-down delay between rails
  • Any timing tolerance associated with the sequencing requirement

Is there a specification for allowable timing skew between these supplies?

2.During startup and shutdown, must the supply rails remain within 0.3 V of each other at all times, including while the rails are ramping?

For example:

  • If one rail reaches its final voltage earlier than another rail during startup, resulting in a temporary voltage difference greater than 0.3 V, is this considered a violation of the power sequencing requirements?
  • Similarly, during power-down, if one rail discharges faster than the others and the voltage difference temporarily exceeds 0.3 V, is this also a violation?

Or is there a separate startup/shutdown tolerance specification that applies?

3.Are there any recommended power supply circuitry or methods to maintain power-sequencing requirements?

Are there TI-recommended methods for handling systems where separate regulators/reference devices inherently have different startup and shutdown behavior?
 
As a potential mitigation, I have reviewed the LAUNCHXL-F28379D design and suggested evaluating whether VDDOSC could be supplied from the same 3.3V LDO as VDDA, VDDIO, and VDD3VFL rather than from the reference IC.
 

Any guidance would be appreciated.

Thank you.

Best regards,

Michael

  • 0
    TI__Mastermind 23551 points

    Hi Michael,

    The expert on this is out of office until July 29th, please expect a delay in response and thank you very much for your patience

    Regards,

    Peter

  • 0 in reply to Peter Luong
    TI__Mastermind 23551 points

    Hi Michael,

    I recommend to power VDDOSC from the same source as the other 3.3V power rails to eliminate any possibly of timing discrepancies.

    VREFHI is not technically considered a power rail, so the only timing requirement is that it should not lead VDDA (and if it does, it cannot exceed 0.3V above VDDA at any time). This same note applies to all analog inputs as well, not exceed VDDA + 0.3V. But there is no issue for VREFHI to lag VDDA and instead, it is recommended for VREFHI to the be the only connection to precision reference to avoid any degradation of the reference voltage. 

    Regards,

    Peter

  • 0 in reply to Peter Luong
    Intellectual 546 points

    Hi Peter,

    Thank you for your response.

    I look forward to the expert's feedback once they are back in the office.

    Based on the waveforms I have been provided, VREFHI appears to lag VDDA during both power-up and power-down.

    During power-up, this means VREFHI remains lower than VDDA at all times.

    During power-down, however, VREFHI remains above VDDA by up to approximately 0.5 V. This voltage difference occurs after both rails have fallen to roughly 1.65 V.

    Would this behavior be considered acceptable? If not, are there any recommendations for improving the power-down behavior?

    Best regards, 

    Michael

  • 0 in reply to Michael V
    TI__Mastermind 23551 points

    Hi Michael, 

    Does the external voltage reference have an EN pin and is this EN pin connected to the 3.3V power rail? If not, one suggestion would be to move to a precision reference that has this pin, thus when there is instability on the power rail or during power down sequence, the reference will shut off the output.

    Also, what is the decoupling cap on the VREFHI pin? If it's 22uF and the 16-bit differential ADC feature is not being used in the system, then it may be better to move to a 1uF or 2.2uF decoupling cap to avoid excess charge being stored in the cap during power down.

    Regards,

    Peter

  • 0 in reply to Peter Luong
    Intellectual 546 points

    Hi Peter,

    Thank you for your support.

    The voltage reference in consideration is that LM4132. This device contains an enable pin, but the voltage needs to be 0.65(Vin), meaning that connecting the pin to the 3.3V rail will not reliably enable the reference output. The current design has the enable pin connected to the 5V rail powering both the 3.3V LDO and the LM4132.

    Do you have any recommendations for this situation?

    Additionally, they are planning on utilizing the 16-bit differential ADC feature and are planning on having 22uF capacitors on the VREFHI line.

    Finally, you previously stated that "there is no issue for VREFHI to lag VDDA ".

    Is there any recommended time delay from VDDA to VREFHI, and is there a maximum delay time requirement (e.g. VREFHI lagging VDDA by ~50ms)?

    In addition to the above questions, I would greatly appreciate any additional suggestions on how to maintain VREFHI as less than VDDA + 0.3V.

    Best regards,

    Michael 

  • 0 in reply to Michael V
    TI__Mastermind 25570 points

    Hi Michael,

    Let me look into this question and get back to you.

    Best Regards,

    Delaney

  • 0 in reply to Michael V
    TI__Mastermind 23551 points

    Hi Michael, 

    It seems the previous suggestions are already covered. For falling edge, I have discussed with few colleagues and the VDDA+/- 0.3V is largely targeted towards runtime operation when all voltage rails are already powered. And it is less stringent during power-on and power-off, we don't have specific data for this though

    These recommendations are targeted towards maintaining device longevity and the impact of slight violations of these specs depend also on the frequency that the device are powered on and off for the operation of the device. 

    Regards,

    Peter

    Regards,

    Peter

  • 0 in reply to Peter Luong
    Intellectual 546 points

    Hi Delaney, Peter

    Thank you for your responses.

    Thank you for clarification on the VDDA+/- 0.3V specification.

    At this point, I believe there are still a few questions and follow-up items from the previous discussion that remain unanswered or only partially addressed. To help keep everything organized, I'd like to summarize the outstanding questions below, along with a few new follow-up questions that arose from the responses received so far.
    ---
    1.What exactly is meant by the requirement that the 3.3V rails be powered simultaneously?
    I could not find any specification defining:
    • Maximum allowed startup delay between rails
    • Maximum allowed power-down delay between rails
    • Any timing tolerance associated with the sequencing requirement
    Is there a specification for allowable timing skew between these supplies?
    ---

    2. Could you confirm if only power-sequencing requirement between VDDA and VREFHI that VREFHI must not exceed VDDA by more than 0.3 V at any time?

    Based on the documentation as well as your previous response, this appears to be the only explicit restriction.

    ---

    3. Could you please confirm whether there are any additional requirements, recommendations, or limitations that must also be considered?

    Are there any recommended or maximum allowable timing delays between VDDA reaching its valid operating voltage and VREFHI becoming valid?

    If so, please provide the applicable limits or recommended design targets.

    ---

    4. If VREFHI rises after VDDA, is any delay interval acceptable provided that the VREFHI ≤ VDDA + 0.3 V requirement is maintained?

    For example, would a delay on the order of tens of milliseconds (e.g., 10 ms, 50 ms, or 100 ms) between VDDA and VREFHI be acceptable?

    ---

    5. Given that the existing VREFHI decoupling capacitor value cannot be changed, and the planned LM4132 voltage reference IC does not support the recommended direct 3.3 V rail connection that you recommended, are there any recommended circuit implementations to ensure compliance with the VREFHI-to-VDDA requirements?

    For example: Recommended voltage reference ICs Use of enable-controlled references Sequencing circuits Supervisors, FET-based solutions, or other methods to ensure VREFHI remains below VDDA + 0.3 V during startup and shutdown.

    ---
    As this issue is now becoming time-critical for my clients PCB design schedule, so I would greatly appreciate any clarification the team can provide at the earliest opportunity.
     
    I look forward to your response.
    Best regards,
    Michael
  • 0 in reply to Michael V
    Intellectual 546 points

    Hello,

    I wanted to follow up on this inquiry and check if there have been any updates.

    Thanks,

    Michael

  • 0 in reply to Michael V
    Intellectual 546 points

    Hello,

    My apologies for the additional follow-up, but due to the time-sensitive nature of this issue, I would greatly appreciate any update you can provide.

    Thank you for your support.

    Best regards,

    Michael