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TMS320F28335: McBSP as SPI Master: Received Data Bit-Shifted During External Flash Read

Ethan Lyu
Intellectual 1225 points

Part Number: TMS320F28335

Hi expert,

One of my KMM DIGIGATE is currently using the McBSP module on the TMS320F28335 DSP as an SPI Master to communicate with an external SPI Flash memory. To verify their software read/write configuration, they are attempting to read the Flash ID.
However, the received data bits are consistently shifted (both left and right shifts occur depending on the software configuration) compared to the expected correct values. For example, the expected Flash ID is 0xC2 20 1B, but the actual value read by the DSP is 0xE1 10 0D.
Here are the details and troubleshooting steps the customer has taken so far:
  1. Digital Loopback Test Passed: The official TI digital loopback (DLB) example code was previously tested on the customer's custom board and worked perfectly. However, as soon as loopback is disabled (McbspaRegs.SPCR1.bit.DLB = 0) to communicate with the external Flash, the bit-shifting issue occurs.
  2. SPI Mode Traversal Failed: The customer has reviewed technical posts regarding McBSP transmit delays, but their primary issue lies on the receive side (MISO/DR). When CLKSTP is set to 2 or 3, they traversed all four SPI modes (combinations of CLKXP and CLKRP), but none of them could successfully read the correct data.
  3. Configuration Check: The customer has carefully checked the McBSP section in the TMS320F28335 TRM (Technical Reference Manual). Judging solely by the documentation, they cannot find any obvious errors in their current register configurations.
  4. Oscilloscope Verification: The customer captured the SPI bus waveforms using an oscilloscope during the Flash reply sequence (where the clock starts low and samples on the rising edge). The waveform shows that the physical data sent by the Flash onto the MISO line is perfectly correct and matches 0xC2 20 1B. This confirms that the external Flash is responding correctly, but the McBSP is sampling it at the wrong time.
Question:
Given that the hardware waveforms are correct and the loopback test passes, what could be causing the McBSP receive buffer to capture bit-shifted data from an external device? Are there specific phase/delay registers (like RPHASE, RWDLEN, or clock setup timing) that the customer might have overlooked for external SPI master operation?
 
Best,
Ethan