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TMS320F28335: CBC behaviour in ePWM UP-DOWN count mode

Gonzalo Sanchez
Prodigy 30 points

Part Number: TMS320F28335

Dear community, 

We have some doubts about the trip-zone force cycle-by-cycle behaviour in UP-DOWN count mode. As far as we understand, after setting the TZFRC.CBC bit by software, the only condition that should restart the ePWM outputs is when the counter reaches zero (TBCTR = 0). In up-down count mode, this condition is met only every 2xTBPRD ( two periods).

The thing is, the ePWM modulus seems to be retriggering not only when TBCTR = 0 but also when TBCTR = TBPRD. ¿Does it make any sense? We have observed this behaviour on the oscilloscope.

TZ init (same for empw 2 and 3)

    // Enable TZ1 as one shot trip sources
    EPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;

    // What do we want the TZ1 to do?
    EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
    EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;

    // Enable TZ interrupt
    EPwm1Regs.TZEINT.bit.OST = TZ_DISABLE; 
    EPwm1Regs.TZEINT.bit.CBC = TZ_DISABLE;

ePWM init (same for empw 2 and 3)

    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;//TB_DIV2;   
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.TBPRD = PWMRED;
    EPwm1Regs.TBCTR = 0x0000; 
    EPwm1Regs.TBPHS.half.TBPHS = 0x0000;
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; 
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A
    EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;

    EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // set actions for EPWM1A
    EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;

    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
    EPwm1Regs.DBFED = PWM_DEADBAND_CNT;
    EPwm1Regs.DBRED = PWM_DEADBAND_CNT;

CBC bit setting

    EALLOW;
    EPwm1Regs.TZFRC.bit.CBC = 1;   
    EPwm2Regs.TZFRC.bit.CBC = 1;
    EPwm3Regs.TZFRC.bit.CBC = 1;
    EDIS;

We are setting the CBC bits on the GPIO ISR (gpio_xint1_isr) when an external condition is detected on the PIN (falling edge) and in the main loop if the condition persists (PIN low). 

 

  • 0
    TI__Intellectual 1830 points

    Hi Gonzalo,

    An EPWM expert will get back to you.

    Regards,
    Harisyam

  • +1
    TI__Expert 3340 points

    Hi Gonzalo,

    Per the TMS320F28335 Technical Reference Manual, the cycle-by-cycle trip condition is cleared when TBCTR = 0x0000 1. The documentation states:

    "The specified condition on the pins is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x0000) if the trip event is no longer present."

    So yes — in up-down count mode, the CBC trip should only auto-clear at CTR=0, which occurs once every full symmetrical period (2×TBPRD counts).

    Why You're Seeing Retrigger at TBCTR=TBPRD

    The behavior you observe is most likely caused by your software continuously re-forcing the CBC trip. You stated:

    "We are setting the CBC bits on the GPIO ISR (gpio_xint1_isr) when an external condition is detected on the PIN (falling edge) and in the main loop if the condition persists (PIN low)."

    Here's what's happening:

    1. CTR=0: The CBC trip auto-clears → action qualifiers resume → outputs retrigger (expected).
    2. CTR=TBPRD: Your CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD causes the shadow-to-active compare register load at both CTR=0 and CTR=TBPRD 2. When the compare value loads at TBPRD and the action qualifier fires (since AQCTLA updates are immediate 3), the output momentarily reasserts before your main-loop code re-forces TZFRC.CBC=1.

    This creates the appearance of a retrigger at TBPRD — it's actually a brief output glitch between the action qualifier event and your software re-applying the trip.

    Recommendations

    1. Try to change the compare load mode to CC_CTR_ZERO only:

      EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load only at CTR=0
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

      This eliminates the TBPRD load event that can cause the action qualifier to momentarily reassert the output.

    2. Ensure TZCTL writes are inside EALLOW/EDIS — the TZCTL register is EALLOW-protected. If the writes during initialization were not protected, the trip action may not be properly configured 4.

    1. TMS320F28335 TRM - Trip-Zone CBC Section
    2. TMS320F28335 TRM - Counter-Compare Submodule
    3. E2E: AQCTLA Register Update Timing
    4. E2E: TZFRC Does Not Work Properly