TMS320F2800157: ADC stability

Hello John,

Your implementation looks good as far as VREFHI cap location is concerned.  Filter cap is right next to the VREFHI pin and via'd to GND with very minimal trace.  What may be of concern are the traces next to VREFHI pin. If the diagonal trace above VREFHI pin is noisy (e.g. digital pin that switches frequently), it may adjacently couple to the VREFHI terminal.  Changing the cap tolerance won't actually help since cap has enough charge to act as local reservoir for the charge to stabilize.  What is more critical is the dielectric stability over the operating range. X5R type capacitors are best suited for VREFHI filtering as they are more stable over temperature compared to.

Have you also checked the input impedance and sample and hold duration (ACQPS) settings?  ACQPS setting is dependent on the input impedance.  If there is insufficient sample and hold time allowed for the sampling cap to settle, then the converted data will be inaccurate.  What type of signal is being sampled and what are the impedances present on this signal path feeding to the analog input?

Regards,

Joseph

Hi Joe,

Good points.

My system samples 16 inputs on a 1mS interval, so I bumped the ACQPS sample and hold from 10 to 512/channel.  All 16 inputs are driven by LMV324 op amps with a 2.2k/3.3K voltage divider to adjust from 5V to 3.3.  This calculates to an effective 1.3K input impedance.  Given the relative slow sampling I'm not seeing this as a problem.

The 4 signals between pins 20 and 21 are analog, and generally clean.  I believe that I will move them out of this channel and put the pour that the LaunchPad uses to insure low noise.

My design is updating a TMS320F2809 that's been in the field for 15 years.  In reviewing the VREF, I found something quite peculiar in that VREFHI and VREFLO are terminated in a 2.2uF to ground as shown below.  This system is quite stable, but I can't find any of the reference design information to determine this is something I should consider doing on the 2800157.  Any thoughts?

Hello John,

John Treubig said:

My design is updating a TMS320F2809 that's been in the field for 15 years.

I'm assuming that when migrating the TMS320F2809 to TMS320F280015x, the ADCs are also configured to be operating in internal VREF mode.  As such, an external 2.2uF cap is required as the filter capacitor for the internal bandgap (as it is impractical to add that internally to the chip) connected from VREFHI to VREFLO, which is the same requirement as the older TMS320F2809.

Regards,

Joseph

Hi Joseph,

Thanks and I understand.

I'm now attempting to try to filter some external noise by longer sampling/averaging.  In debugging through, I start with the inputs at zero and then apply a resistor divider at a set voltage.  I've got an array that is used to average shown below.  Notice that it takes 5 samples (first sample at 017A) to arrive at the correct value.  Can you help me understand why?

Hello John,

Would it be possible for you to share the configurations used in the device, like SYSCLK, ADCCLK (or the prescaler), ACQPS (setting time register value), ADC channel being sampled, trigger frequency and the resistor divider resistances at the ADC input?  Hopefully these will help explain the results you are getting with the conversions.

Regards,

Joseph

Hi Joseph,

Sure

SYSCLK = 50 Mhz

ADCCLK = 50Mhz/4

ACQPS = 512

ADC channel being sampled = A1 (pin 18)

trigger frequency = 1 mS (1kHz)

The divider is 1.5K totem pole that results in 2.52 volts input to MES_TREND.

Thanks John.  Any reason running the F2800157 at 50MHz SYSCLK?  Just a side note but you can actually run the part at 120MHz, have ADC prescaler of 2 to get the ADC to run at 60MHz (120/2)  Running at these clock rates should give you better throughput and minimum execution time if you have control loops.

I see there is only a 1.5K ohm divider at the input.  It would help to put a small cap at the input side for signal filtering.  If you are converting a slow signal or DC, try first with a 1nF or 2nF to see if it helps stabilize conversions.  If dynamic signal, i'd have to see the input network schematics (any resistor divider + filters + caps) so i can calculate the sampling time.

By the way, ACQPS is a 9-bit register [8:0], so setting a value of 512 will actually set this register to 0

Regards,

Joseph