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TMS320F2800157: ADC stability

John Treubig
Prodigy 165 points

Part Number: TMS320F2800157
Other Parts Discussed in Thread: LMV324, TMS320F2809

Hi,

I've a TMS320F2800157 design that I've followed all the guidelines that I can find for ADC layout 

  • VREFH using internal 1.65V reference
  • 2.2uF cap on VREFHI as close the the pads as possible
  • Ferrite filtered VDDA with 2.2uF ceramic cap (3.3 V)

I'm seeing the ADC output varying a few bits and wondering if how to fix.  I have verified the 3.3VDC is rock solid and the analog pin is the same.  

I am questioning my layout around VREFH/VREFL and the 2.2uF cap.  

I noticed the layout on the 00157 LaunchPad insures that there's a plane tied to the 2.2uF cap (C39 is directly connected on the chip level shown below).  

Screenshot 2026-08-06 164258.png

Is this better than my implementation (C14 is viaed to ground within the board.  VREFL is also viaed to ground within the board)?

Screenshot 2026-08-06 164630.png

I am using a CAP CER 2.2UF 10V X5R 0603 cap (+/-20%).  Do I need a tighter tolerance cap?

Your suggestions would be much appreciated.
John

  • 0
    TI__Mastermind 43490 points

    Hello John,

    Your implementation looks good as far as VREFHI cap location is concerned.  Filter cap is right next to the VREFHI pin and via'd to GND with very minimal trace.  What may be of concern are the traces next to VREFHI pin. If the diagonal trace above VREFHI pin is noisy (e.g. digital pin that switches frequently), it may adjacently couple to the VREFHI terminal.  Changing the cap tolerance won't actually help since cap has enough charge to act as local reservoir for the charge to stabilize.  What is more critical is the dielectric stability over the operating range. X5R type capacitors are best suited for VREFHI filtering as they are more stable over temperature compared to.

    Have you also checked the input impedance and sample and hold duration (ACQPS) settings?  ACQPS setting is dependent on the input impedance.  If there is insufficient sample and hold time allowed for the sampling cap to settle, then the converted data will be inaccurate.  What type of signal is being sampled and what are the impedances present on this signal path feeding to the analog input?

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Prodigy 165 points

    Hi Joe,

    Good points.

    My system samples 16 inputs on a 1mS interval, so I bumped the ACQPS sample and hold from 10 to 512/channel.  All 16 inputs are driven by LMV324 op amps with a 2.2k/3.3K voltage divider to adjust from 5V to 3.3.  This calculates to an effective 1.3K input impedance.  Given the relative slow sampling I'm not seeing this as a problem.

    The 4 signals between pins 20 and 21 are analog, and generally clean.  I believe that I will move them out of this channel and put the pour that the LaunchPad uses to insure low noise.

    My design is updating a TMS320F2809 that's been in the field for 15 years.  In reviewing the VREF, I found something quite peculiar in that VREFHI and VREFLO are terminated in a 2.2uF to ground as shown below.  This system is quite stable, but I can't find any of the reference design information to determine this is something I should consider doing on the 2800157.  Any thoughts?

  • 0 in reply to John Treubig
    TI__Mastermind 43490 points

    Hello John,

    John Treubig said:
    My design is updating a TMS320F2809 that's been in the field for 15 years.

    Thumbsup

    I'm assuming that when migrating the TMS320F2809 to TMS320F280015x, the ADCs are also configured to be operating in internal VREF mode.  As such, an external 2.2uF cap is required as the filter capacitor for the internal bandgap (as it is impractical to add that internally to the chip) connected from VREFHI to VREFLO, which is the same requirement as the older TMS320F2809.

    Regards,

    Joseph