TMS320F28335: About using DIVSEL = 3 with PLL enabled

Hi Azad,

Your configuration (PLLCR=6, DIVSEL=3) is explicitly not allowed per TI documentation. The datasheet states the reason clearly:

"A divider at the output of the PLL is necessary to ensure correct duty cycle of the clock fed to the core. For this reason, a DIVSEL value of 3 is not allowed when the PLL is active." 1

When DIVSEL=3 (divide-by-1), the PLL output feeds the core without any output divider. The output divider isn't just for frequency scaling — it serves a critical role in cleaning up the clock duty cycle. Without it, the clock signal delivered to the CPU has an uncontrolled duty cycle, which can cause:

• Setup/hold timing violations within the core logic
• Clock jitter and phase noise that degrades signal integrity
• Metastability in flip-flops that depend on clean clock edges

While your devices may appear to work today, this configuration operates outside the validated design envelope. The risks include:

1. Temperature sensitivity — As junction temperature rises, timing margins shrink. A marginal duty cycle that works at 25°C may cause intermittent failures at elevated temperatures.
2. Part-to-part variation — Different silicon lots may have slightly different PLL characteristics, meaning some units could fail while others don't.
3. Random, hard-to-diagnose failures — Timing violations from poor duty cycle can manifest as corrupted peripheral data, incorrect computation results, or sporadic resets.

The Correct Configuration for 150 MHz:

Per the PLL settings table, DIVSEL=3 is marked as "–" (not available) for all non-zero PLLCR values 2. To achieve 150 MHz correctly:

With a 25 MHz oscillator, the maximum achievable SYSCLKOUT using the recommended DIVSEL=2 is:

• PLLCR=10: (25×10)/2 = 125 MHz

To reach 150 MHz with a 25 MHz oscillator within specification, you would need a 30 MHz oscillator (PLLCR=10, DIVSEL=2 → 150 MHz). This is the standard recommended approach for 150 MHz operation on the F28335.

Even though your current boards appear functional, you are operating outside the device's validated specifications. For production designs — especially those exposed to wide temperature ranges or long field life — you should migrate to a 30 MHz oscillator with PLLCR=10 and DIVSEL=2 to achieve 150 MHz within the documented safe operating region 1 2.

Have you considered whether your application can tolerate running at 125 MHz (25 MHz × 10 / 2) as an interim fix, or would switching to a 30 MHz oscillator be feasible for your next board revision?

1. TMS320F28335 Datasheet — PLL-Based Clock Module
2. TMS320F28335 Datasheet — CLKIN Divide Options
3. E2E Forum — Clock setup when setting DIVSEL to 3

Best Regards,

Zackary Fleenor