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TMS320F28379D: Jitter in UPP

Bhargav Jyoti Saikia
Prodigy 131 points

Part Number: TMS320F28379D

Hello team,

We are using TMS320F28379D and exploring to use UPP to drive a 8-bit parallel DAC at 25 MSPS instead of using GPIOs since this will save CPU time. The application requires very strict timing control when the transmission is started and stopped, i.e. it should be very deterministic. The transmission must always start on the same SYSCLK edge every single time. However, even though we are able to use UPP to drive the DAC at the required rate, there is a jitter where the first UPP CLK edge occurs. So, it is not deterministic and failing our purpose.

To test the jitter, inside a while(1) loop, I am making a GPIO high, starting the transmission, then after a delay of 1ms, making the GPIO low again. A part of the code is below:

....

while(1)
    {
        GPIO_writePin(gpio_4, 1);
        hal_f2837xD_freeRtos_UPP_startTransmission();
        DEVICE_DELAY_US(1000);
        GPIO_writePin(gpio_4, 0);
    }
.....

So, the time duration between the GPIO going high and the first edge of any UPP Data pin (I used D0) should be always constant. But when observed in scope the UPP D0 pin edge keeps jittering left and right with respect to the GPIO edge. The jitter is more than 60ns which will kill our application. Our requirement is 0 ns i.e. always constant or no jitter. The yellow signal is the GPIO going HIGH and the blue signal is UPP D0. The actual jitter is more clearly visible in a video but here I attached just a snapshot. The cursors represents the extreme left and right of the jitter. Here, the first rising edge of the Blue signal alligns with the first cursor, but it keeps shifting and allign with the second cursor also. So, it randomly keeps jumping within the limits of the two cursors. But the duration between the two cursors is 61 ns, so the variation is 61ns.

 UPP Jitter.PNG

I also captured the UPP CLK signal instead of UPP D0 with the GPIO. The CLK always keeps coming as long as the device is ON. The rising edge of the UPP CLK never remains at constant duration from the GPIO edge.
I attached the source code which contains three files. Can you please help me in understanding what is causing the jitter and how to eliminate it? 

upp_jitter_test_main.c

hal_f2837xD_freeRtos_upp.h

hal_f2837xD_freeRtos_upp.c

Thank you,

Bhargav Saikia.

  • 0
    TI__Mastermind 26560 points

    Hi Bhargav,

    Let me look into this and get back to you.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 131 points

    Hi Delaney,

    Were you able to understand any reason why this jitter is happening? Is it inherent to the hardware inside the chip and cannot be avoided? My guess is since the clock is continuously coming, the UPP_D0 rising edge can be at any instant relative to the rising edge of the GPIO, hence the jitter. But I am not sure if my understanding is correct. Is there anything that can be done to remove the jitter?

    Thanks,

    Bhargav.

  • 0 in reply to Bhargav Jyoti Saikia
    TI__Mastermind 26560 points

    Hi Bhargav,

    Apologies for the delay. Can you take a look at the uPP specs in the datasheet (section linked here) and measure for these specific delays? These are the timings we guarantee the module to have. 

    Beyond this, the timing of the GPIO could be playing a role here since it is being written with the CPU. Do you have any interrupts enabled during this test that could be messing with the timing of the operations? Could you also confirm that the time between each GPIO pulse you see on the scope is consistent?

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 131 points

    Hi Delaney,

    I forgot to mention that I am not using the START, ENABLE, WAIT signals. I have gone through time specifications that you referred. Actually, the UPP signals are meeting these specs, but that is not a problem. The problem is more like when the transmission is starting relative to the previous instruction. There is a variable time gap which is causing this jitter.

    Apart from the UPP interrupts, no other interrupts are enabled actually. There is no FreeRTOS running and it is just a bare-metal project with a main function and the UPP drivers. I have attached the source files for reference in the first message.

    Thanks,

    Bhargav Saikia.

  • 0 in reply to Bhargav Jyoti Saikia
    TI__Mastermind 26560 points

    Hi Bhargav,

    Ok, thank you for checking the specs. I will reply back soon.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Mastermind 26560 points

    Hi Bhargav,

    To update, I haven't had a chance to look into this further yet and likely won't have any time this week. When I have time next week I am planning to run your test on a board to see if I can replicate the jitter. Apologies for the delay.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 131 points

    Hi Delaney,

    No worries. Let me know if you get any clue. Maybe you can use the same source code that I shared. If you observe in scope, you will see the jitter between the GPIO rising edge and UPP_D0 pin.

    Thanks,

    Bhargav.