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TMS320F28379D: Phase shifts betwenn EPWM modules

Part Number: TMS320F28379D

Hi Team,

Can you help with implementing phase-shift control for my Triple Active Bridge (TAB) converter?

Each leg of the H-bridges is controlled by a single gate driver with two complmentary outputs, so I only need to provide one PWM signal per leg. The complementary signal and analog dead time are generated internally by the gate driver.

My PWM configuration is as follows:

Port 1: Leg A – EPWM1A, Leg B – EPWM1B

Port 2: Leg A – EPWM2A, Leg B – EPWM2B

Port 3: Leg A – EPWM3A, Leg B – EPWM3B

I also need to control the duty cycle of the generated AC square waveform. For this purpose, I operate each ePWM module in up-down counter mode and generate 50% duty-cycle signals for each individual leg.

For example, for Port 1:

EPWM1A is high from counter zero to TBPRD and low from TBPRD back to zero.

EPWM1B is high from CMPA during up-counting to CMPB during down-counting. For example, CMPA = 0.9 × TBPRD and CMPB = 0.1 × TBPRD.

By controlling the overlap between EPWM1A and EPWM1B, I can therefore control the duty cycle of the resulting AC waveform.

My main question concerns the phase shift among EPWM1, EPWM2, and EPWM3. I use EPWM1 as the master and disable its phase-shift loading. Depending on the power-control command, the phase shifts of Ports 2 and 3 relative to Port 1 may need to be either positive or negative.

Currently, I implement:

EPWM_COUNT_MODE_UP_AFTER_SYNC for a positive phase shift

EPWM_COUNT_MODE_DOWN_AFTER_SYNC for a negative phase shift

The problem occurs when the commanded phase shift of Port 2 or Port 3 changes sign (from negative to positive or vice versa). I then need to change the count direction after synchronization, and this transition appears to cause the loss of one PWM cycle.

Could you please advise me on the proper way to implement a seamless transition between positive and negative phase shifts without losing or disturbing a PWM cycle? 

Thanks!

Marvin

  • Hi Marvin, 
    If I am not wrong, the problem is a PWM pulse is missed whenever count direction is changed after synchronization. Am I right? Is it possible for you to share the configuration? Meanwhile I will try to identify any issue from your explanation.
    Thanks
    Praneeth

  • Hi Marvin,
    I need to know your configuration to know the issue. 
    Most probably, from your explanation, it looks like the sync event is causing the counter to be loaded with a value which is greater than the counter value where PWM goes low/high. Basically a compare event is being missed in one period. To overcome this, reconfiguration will be needed. In that cycle, compare value need to be changed initially and then revert back to the desired compare value.in the subsequent cycle.
    Thanks
    Praneeth

  • Hi Praneeth,

    If I understood you correctly, you're suggesting that I should change the counter compare value when performing the phase shift. Is that correct?
    If so, here's my concern: since the action-qualifying function only allows two counter compare values, I don't think I can have PWM A and PWM B both running at 50% duty cycle, phase-shifted relative to each other, in order to create the zero states in my AC waveform.
    Here is the configuration: configuration.zip
    Regards,
    Marvin
  • Hi Marvin,
    I understood your concern. Let me see the configuration and will get back to you tomorrow
    Thanks
    Praneeth

  • Hi Marvin,
    It might be better if EPWM1A,2A,3A,4A,5A,6A channels are used for each leg. And then using counter compare register values (CMPA,CMPB), phase shift among individual PWM pulses can be controlled. UP count mode without phase shift is sufficient with this approach.
    Thanks
    Praneeth