LAUNCHXL-F28P65X: Low Comparator Based ePWM Trip

Sayali Deshmane

Hello Team,

I am trying to use the CMPSS Low Comparator to trip the ePWM1 signal. For testing purposes, I have configured the DAC threshold value to 2048. However, I am unable to observe any trip event on ePWM1 when using the low comparator.

The same trip configuration works correctly when I use the High Comparator, and the ePWM signal trips as expected. Therefore, I would like to understand if there are any additional settings required for the Low Comparator path or if there is any issue in my current configuration.

Could you please review this and suggest the necessary changes or debugging steps?

// Enable CMPSS
Cmpss2Regs.COMPCTL.bit.COMPDACE = 1;

// Low comparator:
// Non-inverting input = CMPINx
// Inverting input = DAC
Cmpss2Regs.COMPCTL.bit.COMPLSOURCE = 0;

// Direct comparator output
Cmpss2Regs.COMPCTL.bit.CTRIPLSEL = 0;

// Enable async path
Cmpss2Regs.COMPCTL.bit.ASYNCLEN = 1; 

Cmpss2Regs.COMPCTL.bit.COMPLINV = 0;

// DAC reference = VDDA
Cmpss2Regs.COMPDACHCTL.bit.SELREF = 0;

// DAC threshold
Cmpss2Regs.DACLVALS.bit.DACVAL = 2048;

    //(Check in Sysconfig for CMPSS2 LOW comparator signal0 which ADC pin is assigned now its A4)
AnalogSubsysRegs.CMPLPMXSEL.bit.CMP2LPMXSEL = 0; // Input Signal 0 

EDIS;

    EALLOW;

    /* Select CMPSS2_CTRIPLon OUT4 MUX3 */
    EPwmXbarARegs.OUT4MUX0TO15CFG.bit.MUX3 = 0;
    
    /* Enable MUX3 contribution to OUT4 */
    EPwmXbarARegs.OUT4MUXENABLE.bit.MUX3 = 1;

    EDIS;

    EALLOW;

// DCAH uses TRIP4
    EPwm1Regs.DCTRIPSEL.bit.DCALCOMPSEL = 3;
    
    EPwm1Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAL_HI;
    
    EPwm1Regs.TZSEL.bit.DCAEVT1 = 1;

    EPwm1Regs.TZSEL.bit.OSHT1 = 1;
    
    EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_HI;
    
    EPwm1Regs.TZEINT.bit.OST = 1;
    
    EDIS;


///////////////////////////////////////////////////////////////////////////


    EPwm1Regs.TBPRD = 12000;                        // Set timer period
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;             // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                       // Clear counter

    //
    // Setup TBCLK
    //
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm1Regs.CMPA.bit.CMPA = 6000;

    //
    // Set actions
    //
    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;             // Set PWM1A on CAU
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;           // Clear PWM1A on CAD

Thank you for your support.

10 days ago

0 Sayali Deshmane 10 days ago

Prodigy 145 points

Hello Team,

I can observe the same behavior in above code with the low comparator as I see with the high comparator. Even after configuring the low comparator, the output response appears identical to that of the high comparator. Could you kindly let me know why this behavior is occurring and if there is anything I may have missed in the configuration?

0 Fleenor 9 days ago in reply to Sayali Deshmane

TI__Mastermind 38323 points

Hi Sayali,

I can see several issues in your code that explain why the low comparator trip behaves identically to (or doesn't work independently from) the high comparator. Let me walk through them.

Issue 1: Wrong DAC Control Register for the Low Comparator

You are writing to COMPDACHCTL.bit.SELREF to set the DAC reference. However, COMPDACHCTL controls the High comparator's DAC. The Low comparator's DAC is controlled by COMPDACLCTL. You need:

Cmpss2Regs.COMPDACLCTL.bit.SELREF = 0;  // DAC reference = VDDA for LOW DAC

Without this, the low DAC may not be configured with the correct reference, and its output could be indeterminate.

Issue 2: Low DAC Shadow-to-Active Load Not Enabled

The low DAC value register (DACLVALS) is a shadow register. You must ensure the shadow-to-active load mechanism is configured in COMPDACLCTL. Verify that the DACSOURCE and SWLOADSEL bits are set appropriately so the value you write to DACLVALS.bit.DACVAL = 2048 actually propagates to the active register. A typical configuration:

Cmpss2Regs.COMPDACLCTL.bit.DACSOURCE = 0;    // Use DACVALS as source (not ramp)
Cmpss2Regs.COMPDACLCTL.bit.SWLOADSEL = 0;    // Load on SYSCLK

Issue 3: ePWM Digital Compare Path Mismatch

Your code routes the XBAR output to TRIP4 (OUT4) and then selects it via DCALCOMPSEL = 3. However, you then configure:

EPwm1Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAL_HI;

This uses the DCAL (Digital Compare A Low) path. But your trip selection register sets DCALCOMPSEL, which feeds the DCAL input. Verify that DCALCOMPSEL = 3 correctly maps to TRIP4 for your device — on F28P65x, DCALCOMPSEL value 3 corresponds to TRIPINput4. This part appears correct, but confirm by cross-referencing the TRM's DCTRIPSEL bit-field encoding.

Also note: you have TZSEL.bit.OSHT1 = 1 which enables TRIPIN1 as a one-shot source — this is a separate trip input and may be causing unintended trips if TRIPIN1 is active. If you only want the DCAEVT1-based trip, consider clearing this:

EPwm1Regs.TZSEL.bit.OSHT1 = 0;  // Disable unless TRIPIN1 is intentionally used

Issue 4: Analog Pin Mode Must Be Explicitly Enabled

Ensure the analog input pin (A4 in your case) has analog mode enabled. Without this, the digital I/O buffer can interfere with the analog signal 1:

GPIO_setAnalogMode(0, GPIO_ANALOG_ENABLED); // Enable analog mode on the CMPSS input pin

Recommended Debug Steps

Fix COMPDACLCTL — configure the low DAC reference and shadow load as shown above.
Read back COMPSTS — poll Cmpss2Regs.COMPSTS.bit.COMPLSTS to confirm the low comparator output is actually toggling when your input crosses the 2048 threshold 1.
Use async mode during debug — you already have ASYNCLEN = 1, which is correct. Keep this during bring-up to eliminate filter/sync delays 1.
Remove TZSEL.bit.OSHT1 — isolate the trip source to only DCAEVT1 so you can confirm the low comparator path independently.
Be aware of the F28P65x ePWM clock divider errata — your configuration uses HSPCLKDIV = TB_DIV4 and CLKDIV = TB_DIV4. A known silicon errata states that software-forced trip actions may be missed when EPWMCLKDIV ≠ 1 2. While your trip is hardware-driven (not software-forced), keep this in mind if you test with TZFRC.

Best Regards,

Zackary Fleenor

C2000™︎ microcontrollers

C2000 microcontrollers forum