Part Number: TMS320F28388D
Hi Experts,
My cusotmer is seeing an unexpected state changes in the T-Format encoder interface. This issue only happens on some of the encoders. (specific vendor).
Blow is a waveform capture of the issue:
The purple and blue is the TX (to encoder) and RX of the SPI.
The Green is the SPI clock.
The Orange (GPIO1) 1 is the S0 state of the main FSM
The Yellow(GPIO91) is the Couter1.Match2 which triggers the FSM to flip
As you can see in the waveform. There is a period that the SPI clock is missing, this is likely because the FSM is in the wrong state (idle). Which means the FSM is triggered from RECEIVE_DATA to IDEL too early. In fact, you may see an unepxected Couter1.match2 signal which triggers the FSM in the period which SPI clock the missing.
In all, the error should be expected match2 signal -> FSM transiti to IDLE earliy -> clock is missing.
The question is that what might cause the unexpected match2 singal?
Note that this only happens on a specific encoder vendor. The same software works fine on other encoder vendors. Even for encoders from this vendor, the error only happens on some of the cycles.
Regards,
Hang
